Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory
Reexamination Certificate
1999-08-23
2001-06-19
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Including memory
C377S034000, C377S109000
Reexamination Certificate
active
06249562
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to electronic counters and more specifically to a monotonic digit counter optimized for flash implementation.
BACKGROUND OF THE INVENTION
Non-volatile counters are used in various electronic applications. One application utilizing non-volatile counters is the field of electronic commerce in which it is important to order financial transaction in a definite sequence. In such applications, it is important that the counting function be robust in order to withstand hardware and/or software failures. In sensitive applications, such as electronic commerce, it is also necessary for the counting function to be secure against unauthorized intrusion and security breaches. This need for secure counting functions against alteration of the count data is important in networked computer applications. It is desirable that a monotonic counter efficiently provide the count for a particular application and have a sufficiently high count rate. Thus, the counter should count high enough and fast enough for the application in which it is used. It is also desirable that counters retain count data in the absence of power, in the event of power failure.
One prior art method of implementing digital counter circuits is to use a battery or similar power supply in conjunction with a binary, digital counter circuit. However, such counters are disadvantageous in that they often are expensive and relatively unreliable. Battery packed circuits typically occupy a relatively large amount of circuit or device space and impose high count costs. Moreover, batteries are prone to failure and discharge, and must be constantly monitored and periodically replaced to prevent loss of the count data. Present binary counters also typically do not allow for user recovery of count data in the event of count interruption due to power loss, thus, reducing the reliability of such circuits.
SUMMARY OF THE INVENTION
A system and method of implementing a digit counter having a plurality of digits, ranging from a least significant digit (LSD) to a maximum positional digit (MPD), is described. In one embodiment, the system comprises switching a single digit for each increment from the LSD to the MPD. Further, after the MPD is switched, for the next increment, resetting the digits from the LSD to the MPD, and moving the LSD and the MPD by one digit, such that the original LSD becomes a higher precedence digit.
REFERENCES:
patent: 4947410 (1990-08-01), Lippmann et al.
patent: 6084935 (2000-07-01), Mather
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Wambach Margaret R.
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