Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-10-15
2001-08-14
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S714000
Reexamination Certificate
active
06275839
ABSTRACT:
FIELD OF INVENTION
The present invention relates in general to an improved data processing system, and in particular to a method and system for adding floating point numbers.
BACKGROUND OF THE INVENTION
As the demand for better computer calculation performance increases, and particularly in regard to extension of floating point unit of next generation by Binary IEEE format which requires the support of JAVA programs, additional Logic is required in the Add-normalization path. The performance timing is most critical for the floating point units and prior art techniques could only achieve an addition of two floating point numbers mostly in three consecutive calculation steps
(1)—adding the mantissas,
(2)—counting the leading zero digits,
(3)—subtract the number of leading zero digits from the exponent to get the normalized exponent result. This work is usually a serialized work, i.e. a subsequent step can be calculated only when the preceding step is completed.
Some improvements to avoid the serialization time delay were presented in U.S. Pat. No. 5,392,228. Here, the normalizer employs a combination of LZA (leading zero anticipation) and LZD (leding zero detection) techniques. The LZA employed has an accuracy of +/− one bit position and thus can nearly determine the position of the leading one before the add result of the mantissas addition is available. Once the main add result is available, a mask is provided from the LZA output which is ANDed with the Add result to provide an accurate determination of the leading one position. This result is passed to both the shifting multiplexers and the exponent adjustment logic to compute the final floating point result. This so called ‘big LZD’ arrangement, however, requires a significantly larger area to implement compared to a strictly serialized implementation.
Despite this additional area consumption which could be tolerated in many applications the previously mentioned normalizer needs a further calculation step to convert the leading zero count into a normalized exponent result.
Further, it does not provide an exact result of the leading zero count and an additional mask operation step is necessary after the main add result is present to obtain the exact leading zero count, thus an additional time delay is required to perform this calculation step.
With the present extension to 128-bit mantissas the time consuming effect of a strictly serialized work would be aggravated, and the previously described normalizer would consume even more area and a larger calculation time.
In view of the above discussion, it should be apparent to those persons of ordinary skill in the art that a need exists for a method and system which saves calculation time.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method and system for adding floating point numbers and for adapting it to the extended Binary IEEE format required to support Java programs without additional latency.
It is another object of the present invention to provide an improved method and system for adding floating point numbers by which the additional calculation time originating from the extension of 64 bit to 128 bit floating point number calculation is compensated.
It is yet another object of the present invention to provide a method and system for fast adding floating point numbers with minimized hardware area required for the calculation time saving.
The foregoing objects are achieved as is now described.
The method according to the present invention defines a method to use the Input Exponent already in the subblocks of the mantissa Addition. Early in the flow of a cycle, there are parts of the Potential exponent result generated and put together using zero detect signals and carry select signals of the Carry Select Adder of the mantissa addition. For the addition of two 128 bit floating point numbers this reduces the number of required logic gates in the timing critical path from about 16 to 12 gates. This allows a faster cycle time and/or less latency and/or more complex functions. The method and system according to the invention can be applied to adders of different mantissa widths, e.g. 32, 64, 256, etc., or different exponent widths, e.g. 8, 10, 12, etc. and further power of radix 2 also.
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patent: 5684729 (1997-11-01), Yamada et al.
patent: 5694350 (1997-12-01), Wolrich et al.
patent: 5875123 (1999-02-01), Dao Trong et al.
Gerwig Gunter
Getzlaff Klaus Jorg
Kroner Michael
International Business Machines - Corporation
Mai Tan V.
Wojnicki, Jr. Andrew J.
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