Electrical computers and digital processing systems: multicomput – Multicomputer data transferring via shared memory
Reexamination Certificate
2005-08-09
2005-08-09
Cardone, Jason D (Department: 2145)
Electrical computers and digital processing systems: multicomput
Multicomputer data transferring via shared memory
C707S793000
Reexamination Certificate
active
06928466
ABSTRACT:
This invention provides a negative cache management system and method for controlling valid and invalid memory component identifiers, and, thereby, accelerates performance of relatively high speed memory components, including hardware and software systems, that operate with storage devices. This invention includes (a) logic to check the cache to determine if a received memory component identifier is invalid, (b) logic to add the invalid memory component identifier to the cache, such as adding a file identifier to the cache when a search in a directory for a file name is unsuccessful, (c) logic to monitor new memory component identifiers being created and to remove an entry from the invalid list if that file identifier later becomes valid, (d) logic to monitor memory component identifiers being deleted or moved and to add an entry from the invalid list if that file identifier becomes invalid, (e) logic to manage the most frequently used invalid memory component identifiers, and (f) logic to manage the most recently used invalid memory component identifiers.
REFERENCES:
patent: 5008820 (1991-04-01), Christopher, Jr. et al.
patent: 5390318 (1995-02-01), Ramakrishnan et al.
patent: 5649156 (1997-07-01), Vishlitzky et al.
patent: 5742817 (1998-04-01), Pinkoski
patent: 5745778 (1998-04-01), Alfieri
patent: 5778430 (1998-07-01), Ish et al.
patent: 6014667 (2000-01-01), Jenkins et al.
patent: 6049850 (2000-04-01), Vishlitzky et al.
patent: 6094706 (2000-07-01), Factor et al.
patent: 6314493 (2001-11-01), Luick
patent: 6332158 (2001-12-01), Risley et al.
patent: 6370549 (2002-04-01), Saxton
patent: 6453319 (2002-09-01), Mattis et al.
patent: 6453354 (2002-09-01), Jiang et al.
patent: 6490666 (2002-12-01), Cabrera et al.
patent: 6658536 (2003-12-01), Arimilli et al.
patent: 2003/0200197 (2003-10-01), Long et al.
Pei Cao et al., “Maintaining strong cache consistency in the world wide web”, IEEE Transactions on Computers, vol. 47, iss. 4, pp. 445-457, Apr. 1998.
Zhu, H. et al., “Class-based cache management for dynamic web content”, IEEE INFOCOM 2001, vol. 3, pp. 1215-1224, Apr. 2001.
Bulka Dov
Nair Manoj
Cardone Jason D
Cortina A. Jose
Daniels Daniels & Verdonik, P.A.
EMC Corporation
Perkins R. Kevin
LandOfFree
Method and system for identifying memory component... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for identifying memory component..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for identifying memory component... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3523395