Method and system for HSDPA bit level processor engine

Details Method and system for HSDPA bit level processor engine Method and system for HSDPA bit level processor engine

2006-02-14

2010-02-23

Cho, Hong (Department: 2419)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

07668188

ABSTRACT:
Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

REFERENCES:
patent: 6700867 (2004-03-01), Classon et al.
patent: 7328332 (2008-02-01), Tran
patent: 2005/0053168 (2005-03-01), Song et al.
patent: 2005/0201283 (2005-09-01), Yoon et al.
patent: 2005/0233754 (2005-10-01), Beale
patent: 2006/0095745 (2006-05-01), Tran
patent: 2006/0095750 (2006-05-01), Nye et al.
patent: 2006/0195773 (2006-08-01), Pisek et al.

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