Method and system for high-speed floating-point operations...

Details Method and system for high-speed floating-point operations... Method and system for high-speed floating-point operations...

2011-03-01

2011-03-01

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S211000

Reexamination Certificate

active

07899860

ABSTRACT:
A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

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