Method and system for high speed floating point exception enable

Details Method and system for high speed floating point exception enable Method and system for high speed floating point exception enable

1992-10-09

1995-04-25

Lall, Parshotam S.

Boots, shoes, and leggings

395800, 395425, 364DIG1, 364DIG2, 3642302, 3642615, 36493148, 36493151, 36493152, 3649411, G06F 928, G06F 930, G06F 1516, G06F 15347

Patent

active

054106575

ABSTRACT:
A method and system are disclosed for implementing floating point exception enabled operation without substantial performance degradation. In a multiscalar processor system, multiple instructions may be issued and executed simultaneously utilizing multiple independent functional units. This is typically accomplished utilizing separate branch, fixed point and floating point processor units. Floating point arithmetic instructions within the floating point processor unit may initiate one of a variety of exceptions associated within invalid operations and as a result of the pipelined nature of floating point processor units an identification of which instruction initiated the exception is not possible. In the described method and system, an associated dummy instruction having a retained instruction address is dispatched to the fixed point processor unit each time a floating point arithmetic instruction is dispatched to the floating point processor unit. Thereafter, the output of each instruction from the floating point processor unit is synchronized with an output of an associated dummy instruction wherein each instruction within the floating point processor unit which initiates a floating point exception may be accurately identified utilizing the retained instruction address of the associated dummy instruction.

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