Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2003-02-24
2004-11-02
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06812724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of detecting defects in an integrated circuit and in particular to a method and system for determining whether a defect exists within an integrated circuit by measuring and graphically evaluating IDDQ current conducted by the integrated circuit.
2. Description of the Related Art
Testing of a semiconductor device is performed to determine if it is a good device or if it contains defects. IDDQ testing has been used to detect faults within an integrated circuit. Quiescent current, commonly referred to as drain to drain quiescent current (IDDQ), is composed primarily of leakage current. Generally, IDDQ testing is a testing technique which discriminates the presence or absence of a fault by monitoring IDDQ because, if an IC suffers from a short-circuiting fault, a bridging fault or the like, then excessive IDDQ flows in a steady state, which proves the presence of a fault.
Conventional IDDQ testing methods include setting a threshold value of the IDDQ current, in which the integrated circuit being tested is failed if the IDDQ current conducted by the integrated circuit exceeds the threshold value. The IDDQ current is measured while inputs to the integrated circuit are driven high or low depending on predetermined states of input test vectors. IDDQ testing includes stepping through many different combinations of input test vectors to exercise the functionality within the integrated circuit.
One of the most difficult elements of IDDQ testing is setting the threshold value. An integrated circuit that draws more current than the threshold value of IDDQ for any input test vector is declared defective. An integrated circuit that draws less current than the threshold value of IDDQ is considered good. If the threshold value is set too high, then integrated circuits that contain defects may be considered good. This decreases the quality level of the integrated circuits considered good. If the threshold value is set too low, then integrated circuits that are free of defects may fail the IDDQ test. This increases the cost of the integrated circuits considered good. Therefore, the determination of the threshold value for IDDQ testing involves a trade-off between the quality and the cost of the integrated circuits which pass the IDDQ testing.
Gattiker and Maly (A. E. Gattiker and W. Maly, “Current Signatures”, Proc. VLSI Test Symposium, pp. 112-117, 1996) proposed a method which eliminates some of the threshold selection problems. Traditionally, testing of an integrated circuit ends as soon as the integrated circuit fails the IDDQ test. Gattiker and Maly proposed that IDDQ values be measured for a complete set of input test vectors. A complete set of input test vectors include enough test vectors to completely exercise the functionality of the circuitry within the integrated circuit being tested. From the measured values of IDDQ, a current signature is generated. The current signature includes an ordering of the IDDQ measurements from the smallest value to the largest value. Gattiker and Maly claim that the magnitude of the measurements is not as important as the shape of a plot of the current signature. If there are no large jumps in the plot of the current signature, then the integrated circuit is designated as good. If the plot of the current signature include any significant jumps or discontinuities, then the integrated circuit is designated as defective. Testing methods using the Gattiker and Maly IDDQ current signature concepts require a complete set of input vector test settings to be applied to the integrated circuit under test and the resultant measured values of IDDQ current for each input vector test setting to be analyzed.
Methods have been described for reducing the input vector test set. Gattiker and Nigh (A. E. Gattiker, P. Nigh, D. Grosch, and W. Maly, “Current Signatures for Production Testing,” Proc. of the IEEE International Workshop on IDDQ Testing, pp. 25-28, October 1996) describe taking a current measurement for the first vector and rejected die based on subsequent vectors producing currents that differed from the first value by some threshold. Thibeault (C. Thibeault, “A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures,” Proc. of the 15
th
VLSI Test Symp., pp. 80-85, April-May 1997) describe taking differences in IDDQ measurements between a vector and the next one to differentiate good and bad chips.
U.S. Pat. No. 5,914,615 describes a method of improving the quality and efficiency of IDDQ testing. The method includes calculating an upper threshold IDDQ value and a lower threshold IDDQ value. The input nodes are driven to a predetermined combination of input voltages and a corresponding IDDQ value is measured. It is determined whether the measured IDDQ value is between the upper threshold IDDQ value and the lower threshold IDDQ value. Alternatively, the upper and lower threshold values are determined as being dependent on a measured mean value of IDDQ for the integrated circuit.
Typical methods for IDDQ testing require a low background current while in the quiescent state. As device characteristics of semiconductors become smaller and more dense, the IDDQ current caused by defects becomes smaller and harder to differentiate from the increasing background leakage current. For example, in submicron devices large background currents in the range of approximately several tens of milliamps (MA) are likely due to short channel lengths.
U.S. Pat. No. 6,239,606 describes a method to perform IDDQ testing in the presence of high background leakage current. In the method, a first quiescent current measurement is taken. At least a portion of a semiconductor device is biased and a second quiescent current measurement is taken. The portion of the semiconductor device that was biased is then unbiased and a third quiescent current measurement is taken. The first, second and third quiescent currents are then compared to determine if a defect exists in that portion of the semiconductor device.
It is desirable to provide an improved method for reliable testing which may include high leakage current.
SUMMARY OF THE INVENTION
The present invention relates to a method and system for detecting defects within an integrated circuit in which one or more parameters of a classifier are determined by graphical evaluation of IDDQ current measurements. An entire set of IDDQ measurements for chip is plotted and referred to as the band diagram, because the current measurements cluster into bands. Parameters of the classifier can include a number of bands for a good integrated circuit, a width of a band for a good chip, a width ratio between a first band and a second band for a good integrated circuit, a separation between bands for a good integrated circuit, a separation ratio between a first pair of adjacent bands and a second pair of adjacent bands for a good integrated circuit, a slope of a band, a variation in a band width, a maximum IDDQ value for a chip, a minimum IDDQ value for a chip, a mean of a band of a chip, a standard deviation of a band of a chip, a lack of activity of IDDQ measurements conducted in the integrated circuit, noise in the IDDQ measurements conducted in the integrated circuit and glitches in the IDDQ measurements conducted in the integrated circuit. The parameters can be customized for the integrated circuit under test. The parameters are determined from graphical evaluation of IDDQ current measurements on an integrated circuit during chip characterization. The parameters can be determined by multi-variable optimization. Thereafter, the determined one or more parameters of the classifier are applied to the integrated circuit under test to detect if the integrated circuit under test is good or defective. The method and system can be used with all types of integrated circuits with or without memories including digital CMOS integrated circuits including integrated circuits with memories and deep submicron integrated circuits with or
Bushnell Michael L.
Rao Lan
Cuneo Kamand
Hollington Jermele
Mathews, Collins Shepherd & McKay, P.A.
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