Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2006-02-28
2006-02-28
Nguyen, Hanh (Department: 2668)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395200, C370S535000, C370S350000
Reexamination Certificate
active
07006509
ABSTRACT:
A method and system for graceful slowlink deletion and subsequent fast link addition in an inverse multiplexing over asynchronous transfer mode (IMA) group are disclosed in which data is received on one or more data links. The received data is written into a buffer for each data link. The data in the buffer for each data link is read faster than the data is written into the buffer. By reading data from a DCB faster than the data is written into the DCB, the differential delay caused by a slow link deletion can be reduced. As such, a fast link, which otherwise could not be added to an IMA group because of the slow link deletion, can now be added without writing over unread data.
REFERENCES:
patent: 5065396 (1991-11-01), Castellano et al.
patent: 5293570 (1994-03-01), Schmidt et al.
patent: 5333132 (1994-07-01), Chuniaud et al.
patent: 5400324 (1995-03-01), Eriksson et al.
patent: 5404354 (1995-04-01), Hayter et al.
patent: 5448572 (1995-09-01), Knox et al.
patent: 5526361 (1996-06-01), Hedberg
patent: 5608733 (1997-03-01), Vallee et al.
patent: 5617417 (1997-04-01), Sathe et al.
patent: 5764637 (1998-06-01), Nishihara
patent: 5970067 (1999-10-01), Sathe et al.
patent: 6002670 (1999-12-01), Rahman et al.
patent: 6148010 (2000-11-01), Sutton et al.
patent: 6198754 (2001-03-01), Nakayama
patent: 6205142 (2001-03-01), Vallee
patent: 6222858 (2001-04-01), Counterman
patent: 6411701 (2002-06-01), Stademann
patent: 6449658 (2002-09-01), Lafe et al.
patent: 6549522 (2003-04-01), Flynn
patent: 6621794 (2003-09-01), Heikkinen et al.
patent: 6678275 (2004-01-01), DeGrandpre et al.
patent: 6680954 (2004-01-01), Cam et al.
patent: 6717960 (2004-04-01), Anesko et al.
patent: WO 90-12467 (1990-10-01), None
patent: WO 93-03569 (1993-02-01), None
I. Widjajat et al., “A High-Capacity Broadband Packet Switch Architecture Vased on Multilink Approach”, MILCOM '92 Communications- Fusing, Command, Control and Intelligence.
-PCT Notification of Transmittal of the International Search Report of the Declaration for the International Application No. PCT/US95/10218, 7 pages (Dec. 5, 1995).
Katsuyuki Yamazaki et al., “ATM Transport with Dynamic Capacity Control for Interconnection of Private Networks”, IEICE Transactions Comm., vol. E77-B No. 3 pp. 327-334 (1994).
Richard Valle et al., “The ATM Forum Technical Committee, Inverse Multiplexing for ATM (IMA) Specification”.
Richard Valle et al., The ATM Forum Technical Committee, Inverse Multiplexing for ATM (IMA) Specification (Final Ballot- Draft #) Dec. 1998.
Jagannatharao Manjunath
Kothandaraman Rajagopalan
Nair Saju
Rangarajan Raja
Blakely , Sokoloff, Taylor & Zafman LLP
Cisco Technology Inc.
Nguyen Hanh
LandOfFree
Method and system for graceful slowlink deletion and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for graceful slowlink deletion and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for graceful slowlink deletion and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3659219