Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-02-16
2002-08-13
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S226000
Reexamination Certificate
active
06434044
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to voltage generation and, more particularly, to voltage generation internal to memory systems.
2. Description of the Related Art
Memory cards are commonly used to store digital data for use with various products (e.g., electronics products). Examples of memory cards are flash cards that use Flash type or EEPROM type memory cells to store the data. Flash cards have a relatively small form factor and have been used to store digital data for products such as cameras, hand-held computers, set-top boxes, hand-held or other small audio players/recorders (e.g., MP3 devices), and medical monitors. A major supplier of flash cards is SanDisk Corporation of Sunnyvale, Calif.
FIG. 1
is a block diagram of a conventional memory system
100
. The conventional memory system
100
provides non-volatile data storage and represents, for example, a memory card (e.g., flash card). The conventional memory system
100
couples to a host
102
. The host
102
can, for example, be a personal computer or an electronic appliance. The memory system
100
includes a memory controller
104
and memory chips
106
and
108
. The memory controller
104
includes a voltage regulator
110
. A host Input/Output (I/O) bus couples the memory controller
104
to the host
102
. The host
102
also supplies a supply voltage V
DD
to the memory controller
104
. The voltage regulator
110
within the memory controller
104
receives the supply voltage V
DD
and regulates the supply voltage to produce a regulated supply voltage V
DDR
. The regulated supply voltage V
DDR
is supplied to each of the memory chips
106
and
108
. The regulated supply voltage V
DDR
is a fixed voltage level (typically within a tolerance) that is supplied to the memory chips
106
and
108
. In this embodiment, the memory chips
106
and
108
require the supply voltage that is supplied to the memory chips
106
and
108
be at a particular voltage level. Since the memory system
100
couples to various different hosts, the supply voltage V
DD
can vary over different voltage ranges, for example, 1.8 volts, 3.3 volts or 5 volts. However, it is typical that current memory chips require that the voltage be 3.3 volts. The voltage regulator
110
ensures that the regulated supply voltage V
DDR
is set at a particular voltage level (e.g., 3.3 volts) regardless of the level of the supply voltage V
DD
.
In any case, the memory chips
106
and
108
require for their operation various different supply voltage levels than the particular voltage level (i.e., V
DDR
) received from the memory controller
104
. Hence, the memory chips
106
and
108
include charge pump circuits
112
and
114
, respectively. The charge pump circuits
112
and
114
receive the regulated supply voltage V
DDR
independently and internally generate additional supply voltage levels for internal use by their associated memory chip. In another embodiment, the memory chips can operate upon receiving different supply voltages when the memory controller provides no voltage regulation. However, in doing so, memory chip design is more complex and optimal performance is lost because memory chips must detect the input supply voltage level and then select a set of operating parameters that correspond to the detected level of the input supply voltage.
One problem with the conventional memory system
100
is that each of the memory chips are required to include charge pump circuitry. The charge pump circuitry not only consumes precious semiconductor die area of the memory chips but also causes substantial noise generation when producing the additional supply voltages. The noise generation can detrimentally affect the sensitive analog portions of the memory chips. Accordingly, the additional noise provided by the charge pump circuitry degrades operational performance of the memory chips.
Thus, there is a need for improved approaches to producing various different supply voltage levels for use by memory chips that provide non-volatile data storage.
SUMMARY OF THE INVENTION
Broadly speaking, the invention relates to techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips). The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to or between memory blocks through a power bus.
The invention can be implemented in numerous ways, such as, a system, apparatus, device, and method. Several embodiments of the invention are discussed below.
As a memory system that receives an external supply voltage from a host, one embodiment of the invention includes at least: a plurality of memory blocks, each of the memory blocks including at least a plurality of data storage elements; and a memory controller operatively coupled to the memory blocks and operatively coupled to receive the external supply voltage when the memory system is operatively connected to the host, the memory controller including at least a voltage generation circuit operable to produce at least a first supply voltage for use by each of the memory blocks. The embodiment of the invention may optionally include a power bus coupled to each of the memory blocks for supplying at least the first supply voltage between the memory blocks.
As a memory system that receives an external supply voltage from a host, another embodiment of the invention includes at least: a plurality of memory blocks, each of the memory blocks including at least a plurality of data storage elements, at least one of the memory blocks further including at least a first voltage generation circuit operable to produce at least one memory-generated supply voltage; a memory controller operatively coupled to the memory blocks and operatively coupled to receive the external supply voltage when the memory system is operatively connected to the host, the memory controller including at least a second voltage generation circuit operable to produce at least one controller-generated supply voltage; and a power bus coupled to each of the memory blocks. The power bus supplies the at least one memory-generated supply voltage between the memory blocks.
As a memory system that receives an external supply voltage from a host, still another embodiment of the invention includes at least: a plurality of memory blocks, each of the memory blocks including at least a plurality of data storage elements, at least one of the memory blocks further including at least a first voltage generation circuit operable to produce at least one memory-generated supply voltage; a memory controller operatively coupled to access the memory blocks; and a power bus coupled to each of the memory blocks. The power bus supplies the at least one memory-generated supply voltage between the memory blocks.
As a data storage device that removably couples to a host unit, one embodiment of the invention includes at least a memory controller; a plurality of memory blocks operatively connected to the memory controller, each of the memory blocks including at least data storage elements; and a power bus operatively supplying different level supply voltages between each of the memory blocks, the different level supply voltages being centrally generated by the memory controller or one of the memory blocks.
As an electronic system, one embodiment of the invention includes at least a data acquisition device, and a data storage device removably coupled to the data acquisition unit. The data storage device stores data acquired by the data acquisition device. The data storage device includes at least: a memory controller; a plurality of memory blocks operatively connected to the memory controller, each of the memory blocks including at least data storage elements; and a power bus operatively supplying different level supply voltages between each of the memory blocks, the different level supply voltages being centrally generated by the memory contr
Cernea Raul Adrian
Conley Kevin M.
Gongwer Geoffrey Steven
Wang Chi-Ming
Wang Yong Liang
Beyer Weaver & Thomas LLP
Hoang Huan
SanDisk Corporation
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