Method and system for generating digital clock signals of progra

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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Details

327149, 327114, 331 57, 331 34, H03L 7099, H03K 513

Patent

active

059202165

ABSTRACT:
A clock generating circuit is provided with a pair of programmable clock dividers coupled to a phase error detector for detecting a phase difference between signals corresponding to reference and clock signals. Frequency change logic produces a frequency adjustment signal that adjusts the frequency of the clock signal to eliminate the phase difference. The frequency adjustment signal is used to control a delay time in a first programmable delay chain. An updated frequency adjustment signal controls a delay time in a second programmable delay chain that receives an output signal of the first programmable delay chain. Signals delayed in the first and second programmable delay chains cause a stable clock signal at a variable frequency to be produced.

REFERENCES:
patent: 5052031 (1991-09-01), Molly
patent: 5075640 (1991-12-01), Miyazawa
patent: 5162746 (1992-11-01), Ghoshal
patent: 5256980 (1993-10-01), Itri
patent: 5329254 (1994-07-01), Takano
patent: 5389843 (1995-02-01), McKinney
patent: 5490182 (1996-02-01), Arai

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