Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2006-12-29
2009-11-10
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S017000, C331S016000, C327S157000
Reexamination Certificate
active
07616069
ABSTRACT:
Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.
REFERENCES:
patent: 5038117 (1991-08-01), Miller
patent: 5151665 (1992-09-01), Wentzler
patent: 6327319 (2001-12-01), Hietala et al.
patent: 2005/0258907 (2005-11-01), Zachan et al.
patent: 2005/0264330 (2005-12-01), Li
Q. Huang and R. Rogenmoser, “Speed Optimization of Edge-Triggered CMOS CircuitsFor Gigahertz Single-Phase Clock,” IEEE JSSC, vol. 31, No. 3, pp. 456-464, Mar. 1996.
H. Huh, Y. Koo, K. Lee, Y. Ok, S. Lee D. Kwon, J. Lee, Joonbae Park, D. Lee, D. Jeong and W. Kim, “Comparison Frequency Doubling and Charge Pump Matching Techniques for Dual-Band Fractional-N Frequency Synthesizer,” IEEE JSSC, vol. 40, No. 11, pp. 2228-2236, Nov. 2005.
S. Pellerano, S. Levantino, C. Samori, and L. Lacaita, “A 13.5-mW 5 GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider,” IEEE JSSC, vol. 39, No. 2, pp. 378-383, Feb. 2004.
J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE JSSC. vol. 24, No. 1, pp. 62-70, Feb. 1989.
M. Kozak and E. Friedman, “Design and Simulation of Fractional-N PLL Frequency Synethesizers,” IEEE ISCAS, pp. 780-783, May 2004.
Broadcom Corporation
Johnson Ryan J.
McAndrews Held & Malloy Ltd.
Pascal Robert
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