Television – Special applications – Flaw detector
Reexamination Certificate
2002-12-16
2004-02-17
Britton, Howard (Department: 2613)
Television
Special applications
Flaw detector
C348S218100, C382S149000
Reexamination Certificate
active
06693664
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to methods and systems for electro-optically detecting fabrication defects, which are random in nature, in semiconductor patterned structures such as a semiconductor wafer featuring integrated circuit dies or chips. In particular, the present invention relates to a method and system for fast on-line electro-optical detection of wafer defects by illuminating with a short light pulse from a pulsed laser, a field of view of an electro-optical camera system having microscopy optics, and imaging, a moving wafer, on to a focal plane assembly (FPA) optically forming a surface of photo-detectors at the focal plane of an optical imaging system, formed from several detector ensembles, each detector ensemble including an array of several two-dimensional matrix photo-detectors, where each two-dimensional matrix photo-detector produces an electronic image featuring a matrix of picture elements (pixels), such that the simultaneously created images from the different matrix photo-detectors are processed in parallel using conventional image processing techniques, for comparing the imaged field of view with another field of view serving as a reference, in order to find differences in corresponding pixels, indicative of the presence of a wafer die defect.
Hereinafter, the term ‘wafer’ refers to, and is generally considered to feature individual patterned structures, known as ‘semiconductor wafer dice’, ‘wafer dice’, or wafer chips’. Current semiconductor technology involves the physical division of a single wafer into identical dies for the manufacture of integrated circuit chips, such that each die becomes an individual integrated circuit chip having a specific pattern, such as a memory chip or a microprocessor chip, for example. The type of chip produced from a given die is not relevant to the method or system of the present invention.
Hereinafter, the term ‘field of view’ refers to that part or segment of, a wafer, in general, and a wafer die, in particular, illuminated by a pulsed laser and imaged by the electro-optical camera system inspection optics in conjunction with the FPA. Accordingly, an entire single wafer die, and therefore, an entire single wafer featuring a plurality of wafer dies, is inspected by sequential imaging of a plurality or sequence of fields of view. The field of view can be considered as the inspection system electro-optical imaging footprint on the wafer or wafer die. Successive fields of view created while the wafer is moving in one direction are referred to as a ‘strip’ of fields of view. Pixels are referred to with respect to forming an image of a field of view by the electro-optical inspection system. As a reference dimension, general order of magnitude of the size of a typically square wafer die within a wafer is 1 centimeter by 1 centimeter, or 10
4
microns by 10
4
microns.
Hereinafter, detection of a ‘wafer defect’ refers to the detection of the presence of an irregularity or difference in the comparison of like patterns of wafer dies or like patterns of fields of view. Current methods and systems of defect detection on wafers are usually based on the analysis of comparing signals obtained from a number of adjacent wafer dies or fields of view, featuring a like pattern. Defects produced during wafer fabrication are assumed to be random in nature. Therefore, defect detection is based on a statistical approach, whereby the probability that a random defect will exist at the same location within adjacent wafer dies is very low. Hence, defect detection is commonly based on identifying irregularities through the use of the well known method of die-to-die comparison. A given inspection system is programmed to inspect the pattern of a wafer die or field of view, typically referred to as the inspected pattern, and then compares it to the identical pattern of a second wafer die or field of view on the same wafer, serving as the reference pattern, to detect any pattern irregularity or difference which would indicate the possible presence of a wafer defect. A second comparison between the previously designated inspected pattern and the like pattern of a third wafer die or field of view is performed, in order to confirm the presence of a defect and to identify the wafer die or field of view containing the defect. In the second comparison, the first wafer die or field of view is considered a reference and the third wafer die or field of view is considered as inspected.
Fabrication of semiconductor wafers is highly complex and very expensive, and the miniature integrated circuit patterns of semiconductor wafers are highly sensitive to process induced defects, foreign material particulates, and equipment malfunctions. Costs related to the presence of wafer defects are multiplied several fold when going from development stages to mass production stages. Therefore, the semiconductor industry critically depends on a very fast ramp-up of wafer yield at the initial phase of production, and then achieving and controlling a continuous high yield during volume production.
Critical dimensions of integrated circuits on wafers are continuously decreasing, approaching 0.1 micron. Therefore, advanced semiconductor wafers are vulnerable to smaller sized defects than are currently detected. Current methods of monitoring wafer yield involve optically inspecting, in-process, wafers for defects and establishing a feedback loop, with appropriate parametric process control, between the fabrication process and the manufactured wafers. To detect smaller sized defects, optical inspection systems need to have higher resolution via scanning wafers using smaller pixel sizes. Scanning a given sized wafer using pixel sizes smaller causes an increase in per wafer inspection time, resulting in decreased wafer throughput, and decreased statistical sample sizes of the number of inspected wafers. Conversely, attempting to increase wafer inspection throughput by using current optical system pixel sizes results in reducing the effectiveness, i.e., resolution, of detecting wafer defects.
In addition to decreasing critical dimensions of wafers, the semiconductor industry is in the process of converting from manufacturing 8-inch wafers to 12-inch wafers. Larger, 12-inch wafers have more than twice the surface area compared to 8-inch wafers, and therefore, for a given inspection system, inspection time per 12-inch wafer is expected to be twice as long as that per 8-inch wafer. Fabricating 12-inch wafers is significantly more expensive than fabricating 8-inch wafers. In particular, costs of raw materials of 12-inch wafers are higher than those of 8-inch wafers. One result of wafer size conversion, is that cost effective productivity of future wafer manufacturing will depend critically upon increasing speed and throughput of wafer inspection systems.
Automated wafer inspection systems are used for quality control and quality assurance of wafer fabrication processes, equipment, and products. Such systems are used for monitoring purposes and are not directly involved in the fabrication process. As for any principle component of an overall manufacturing system, it is important that a wafer inspection method, and system of implementation, be cost effective relative to the overall costs of manufacturing semiconductor wafers.
There is thus a need to inspect semiconductor wafers for wafer die defects, for wafers featuring larger sizes and smaller critical dimensions, at higher throughput than is currently available, and in a cost effective manner.
Automated optical wafer inspection systems were introduced in the 1980's when advances in electro-optics, computer platforms with associated software and image processing made possible the changeover from manual to automated wafer inspection. However, inspection speed, and consequently, wafer throughput of these systems became technology limited and didn't keep up with increasingly stringent production requirements, i.e., fabricating integrated circuit chips from wafers of increasing size and decrea
Britton Howard
Hoffman Wasson & Gitler
Negevtech
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