Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2008-03-04
2008-03-04
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S036000
Reexamination Certificate
active
07340585
ABSTRACT:
A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 27, 29, 31) coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.
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Bilski Goran
Ganesan Satish R.
Prabhu Usha
Wittig Ralph D.
King John J.
Pan Daniel H.
Xilinx , Inc.
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