Method and system for false path analysis

Details Method and system for false path analysis Method and system for false path analysis

2011-06-07

2011-06-07

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S111000, C716S136000, C716S126000

Reexamination Certificate

active

07958470

ABSTRACT:
Disclosed are methods and systems for performing false path analysis. In one approach, the methods and systems identify a set of zero or more false paths based upon both implementation-specific design data and non-implementation-specific design data. In some approaches, disclosed are methods and systems for performing automated gate-level static timing false path analysis, identification, constraint generation, and/or verification using architectural information. Static timing paths at the gate-level can be linked to the architectural information via mapping techniques found in equivalence checking (EC). The gate level static timing paths can be analyzed in the context of the architectural information to identify false paths.

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