Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-08-23
2011-08-23
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S111000, C716S119000, C716S123000, C716S129000, C716S130000, C716S135000, C716S138000
Reexamination Certificate
active
08006212
ABSTRACT:
One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value.
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Chiang Charles C.
Sinha Subarnarekha
Kik Phallaka
Park Vaughan Fleming & Dowler LLP
Synopsys Inc.
Yao Shun
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