Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1998-04-13
1999-06-29
Picardat, Kevin M.
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
438 14, 438 17, G01R 3126, H01L 2166
Patent
active
059181079
ABSTRACT:
A method and system for fabricating electronic assemblies, such as multi chip modules, which include wire bonded semiconductor dice, are provided. Initially, dice having bond pads, and a substrate having corresponding bond pads, are provided. Using a wire bonding process, bonded connections are made between the bond pads on the dice, and the bond pads on the substrate. During the wire bonding process, electrical continuity in the bonded connections can be evaluated. Following wire bonding, but prior to subsequent processing of the assemblies, quick functionality tests can be performed to evaluate other electrical characteristics of the assemblies (e.g., gross functionality, open/short, pad leakage, cell defects). This permits defective assemblies to be identified prior to further processing. Once the assemblies have been completed, full functionality and parametric tests can be performed. An assembly for performing the method includes a conventional wire bonder; a tester having test circuitry for performing the required tests; and an electrical connector for establishing temporary electrical communication with the assembly.
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Fogal Rich
Heppler Steve
Collins Deven
Gratton Stephen A.
Micro)n Technology, Inc.
Picardat Kevin M.
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