Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Using epitaxial lateral overgrowth
Reexamination Certificate
2002-06-04
2003-07-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Using epitaxial lateral overgrowth
C438S317000, C438S318000, C438S312000, C438S605000, C438S607000
Reexamination Certificate
active
06589850
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of semiconductor fabrication. More particularly, the present invention is in the field of fabrication of bipolar transistors.
2. Related Art
Bipolar transistors are commonly used in electronic devices and, in particular, in radio frequency applications. A particular type of bipolar transistor, which is used as an example in the present application, is the silicon-germanium (“SiGe”) heterojunction bipolar transistor (“HBT”) in which a thin layer of silicon-germanium is grown over the bipolar transistor's collector region to operate as the base of the bipolar transistor. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon-only bipolar transistor, for instance. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the silicon-germanium HBT.
The higher gain, speed and frequency response of the silicon-germanium HBT are possible due to certain advantages of silicon-germaniurn, such as a narrower band gap and reduced resistivity. These advantages make silicon-gernanium devices more competitive than silicon-only devices in areas of technology where superior speed and frequency response are required.
Reference is now made to
FIG. 1
, which illustrates bipolar structure
100
, which in the present example is a silicon-germanium HBT structure. As shown, structure
100
includes, among other components, collector
130
, silicon-germanium base
120
, and emitter
140
. In structure
100
, collector
130
is N type single-crystal silicon and base
120
is P type single-crystal silicon-germanium. As will be discussed in greater detail below, base
120
can be fabricated epitaxially, for example, in a reduced pressure chemical vapor deposition process (“RPCVD”), to grow a silicon-germanium film over top surface
132
of collector
130
. A suitable dopant, such as boron, is typically introduced during the silicon-germanium film growth to attain the desired electrical properties of the base.
Continuing with
FIG. 1
, structure
100
further includes emitter
140
, which is situated above and forms a junction with base
120
, and which is comprised of N type polycrystalline silicon. The interface between emitter
140
, base
120
, and collector
130
is the active region of the NPN silicon-germanium HBT, i.e., structure
100
. In structure
100
, dielectric segments
142
provide electrical isolation to emitter
140
from base
120
.
As further illustrated in
FIG. 1
, buried layer
134
, which is composed of N+ type material, is formed in semiconductor substrate
110
. Collector sinker
136
, also composed of N+ type material, is formed by diffusion of heavily concentrated dopants from the surface of collector sinker
136
down to buried layer
134
. Buried layer
134
and collector sinker
136
provide a low resistance electrical pathway from collector
130
through buried layer
134
and collector sinker
136
to a collector contact (not shown). Deep trench structures
133
and field oxide regions
138
provide electrical isolation from other devices on semiconductor substrate
110
.
Referring now to
FIG. 2
, graph
200
illustrates the doping profile of the base in an exemplary silicon-germanium HBT, such as the NPN silicon-germanium HBT structure of structure
100
in FIG.
1
. In graph
200
, y-axis
202
plots the concentration level of materials (e.g., germanium and other dopants) that are deposited along with silicon over the collector as part of growing the base, and x-axis
204
plots the thickness of the base as the deposition proceeds. Thus, the origin (i.e., the intersection of y-axis
202
and x-axis
204
) of graph
200
corresponds to the top surface of the collector over which the silicon-germanium base is grown, at the point where fabrication of the base is to begin with the deposition of silicon only.
Continuing with
FIG. 2
, at point A on x-axis
204
, germanium is introduced into the deposition process and grows along with the silicon over the collector. Profile
206
illustrates the doping profile of the germanium. At point B, a suitable dopant is introduced into the mix with the silicon and germanium, and the concentration level of the dopant is shown by profile
208
. The dopant can be boron, for example. By the time the thickness of the base reaches point C, the germanium has been ramped down, and the deposition then continues with silicon and the dopant only. Finally, at point D, the growth of the base in the present example is complete and, as such, point D corresponds to the interface between the base and emitter.
Conventional methods for growing the base in a bipolar transistor generally involve a series of steps. In one approach used for forming the silicon-germanium base in a SiGe HBT, for example, a wafer having a transistor region over which the silicon-germarnium base is to be grown is initially baked in a reactor chamber at approximately 900° C. for approximately five minutes. Subsequently, the chamber is cooled down to between 600° C. and 750° C. so that the desired base materials, for example silicon-germnanium and boron, can be deposited. According to this method, the formation of the base typically requires between approximately five and ten minutes to complete, after which time the wafer is removed from the reactor chamber.
Once the base has been formed and the completed wafer has been removed, the chamber has to undergo extensive conditioning in preparation for the next wafer. The conditioning is necessary due to, for instance, the accumulation of materials on the chamber wall from previous deposition procedures that can adversely impact the processing of subsequent wafers. More specifically, a primary concern is the presence of residual dopant materials, such as boron, on the chamber walls which can contaminate subsequent wafers and compromise the electrical properties of the base layer formed on these subsequent wafers.
To eliminate the threat of contaminating subsequent wafers, a chamber etching step is needed after the processing of each wafer to remove the undesired materials from the chamber. Typically, the chamber temperature has to be raised to approximately 1100° C., and an etchant, for example HCI gas, is supplied to etch the dopant or undesired materials, along with the silicon and germanium, from the chamber walls. Once the chamber has been cleaned, the etchant is evacuated out of the chamber. The chamber temperature has to then be lowered to approximately 900° C. before the next wafer can be processed.
The need to clean the chamber after each wafer introduces a significant time and cost budget on manufacturers. The time required to clean the chamber translates to lower throughput and productivity and to higher manufacturing cost. Some manufacturers have tried to increase throughput by, for example, baking the wafers in a separate bake chamber and coupling the bake chamber to multiple epi chambers, wherein deposition of the base can occur. In this manner, wafers can be processed more quickly since one epi chamber can be depositing while the other epi chamber is being cleaned. The separate bake chamber supplies a steady number of wafers to the epi chambers. However, with this approach, an epi chamber still needs to be cleaned after every wafer to remove the undesired materials accumulated on the chamber walls. Manufacturers have also tried to increase production by simply investing in more equipment, such as more epi and bake chambers. Approaches known currently, however, remain inefficient. Whether due to lower throughput or due to higher costs as a consequence of the need for more equipment, conventional processing methods impose significant burdens on manufacturers.
There is thus a need in the art for an approach for fabricating bipolar transistors, such as SiGe HBT transistors, that is more efficient than conventional approaches, and which will increase thro
Farjami & Farjami LLP
Kennedy Jennifer M.
Newport Fab LLC
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