Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
2001-08-08
2002-10-29
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S195000, C438S264000
Reexamination Certificate
active
06472327
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory arrays, and more particularly to a method and system for etching tunnel oxide to reduce undercutting during memory array fabrication.
BACKGROUND OF THE INVENTION
Achieving higher densities on a memory chip is a common goal during chip fabrication. The various processes and techniques used to manufacture chips have therefore become increasingly important. Part of the process involved in manufacturing a flash memory array, for example, requires generating select gate transistors and word-line transistors on a silicon substrate with different gate oxide thickness, as shown in
FIGS. 1 and 2
.
FIG. 1A
is a top view of a portion of a flash memory array
10
showing a select gate region
12
of the chip where select gates
14
are located and a word-line region
16
where word-line gates
18
are located.
FIG. 1B
is a cross-sectional view of the memory array
10
. Both the select gate
14
and word-line gate
18
are grown over a gate oxide layer, but the select gate
14
requires a thicker layer of gate oxide than does the word-line gate
18
. The process used to build this array structure
10
determines how close the gates
14
and
18
can be located on the substrate
22
.
FIGS. 2A-2B
are cross-sectional views of the substrate showing a conventional process for forming the select gate region
12
and the word-line region
16
. First, a layer of gate oxide is applied to both regions of the substrate to a depth of approximately 150 angstroms, followed by a deposition of a tunnel oxide mask
24
, as shown in FIG.
2
A.
Thereafter, a wet-etch process is performed to remove the gate oxide
20
in the word-line region
16
that is not covered by the tunnel oxide mask
24
, as shown in
FIG. 2B. A
conventional wet-etch process is isotropic or unidirectional meaning that the material being etched is etched in all directions at the same rate. After the gate oxide
20
is removed from the word-line region
16
, the tunnel oxide mask
24
is removed. This is followed by tunnel oxidation where a layer of gate oxide is grown over both regions.
Referring again to
FIG. 1B
, due to the growth rate difference of the gate oxide
20
and the substrate
22
, the process will result in a select gate oxide
28
having a thickness of approximately 180 angstroms, and a tunnel oxide
30
having a thickness of approximately 90 angstroms, as shown in FIG.
1
B. Thereafter, the select gate
14
and word-line gate
18
are built on top of the gate oxides
28
and
30
.
Referring again to
FIG. 2B
, although the wet-etch process effectively removes the gate oxide
20
vertically from the word-line region
16
, the gate oxide
20
is also removed horizontally due to the unidirectional nature of the wet-etch process. This results in a significant undercut
32
of the gate oxide
20
underneath the tunnel oxide mask
24
. In the example above, for instance, removing 150 angstroms of the gate oxide
20
over the wordline region
16
may require that the wet-etch process be set to remove 200 angstroms to ensure that all the gate oxide
20
is removed. This will result in a 200 angstrom undercut
32
.
If this undercut
32
reaches the location of the select gate
14
, it will cause problems in the circuit. In order to prevent this, a very strict lithographic overlay requirement is needed to allow adequate separation between the edge of the tunnel oxide mask
24
and the location of the select gate
14
. Because of this separation, it is not possible to pack the transistors on the chip as densely as would otherwise be possible.
Another method for removing material, other than a wet-etch process, is a dry-etch process. A dry-etch is an anisotropic process whereby ions and reactive gas species are used to remove material. Although a dry-etch is anisotropic, meaning that it removes material directionally, it has not traditionally been used to remove gate oxide in the above described process because the high-energy ions damage the gate area of the substrate and degrade device characteristics.
Accordingly, a method for minimizing the undercut
32
of gate oxide and relaxing the lithographic overlay requirement between the tunnel oxide mask
24
and a select gate
14
is needed. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begins by depositing an oxide on a substrate, followed by a deposition of a mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the oxide uncovered by the mask, which minimizes oxide undercut.
According to the system and method disclosed herein, the present invention allows the lithographic overlay requirement between the tunnel oxide mask and a select gate to be relaxed, and enables denser memory arrays.
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Chang Mark S.
Fang Hao
Ko King Wai Kelwin
Advanced Micro Devices , Inc.
Fahmy Wael
Garcia Joannie Adelle
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