Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2005-02-08
2005-02-08
Paladini, Albert W. (Department: 2125)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C703S002000, C703S014000, C716S030000
Reexamination Certificate
active
06853969
ABSTRACT:
A system and method for estimating interconnect delay are disclosed that include determining inductance of an interconnect. A transfer function is determined using the inductance, and two poles of the transfer function are determined. An interconnect delay is estimated using the two poles.
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patent: 5313398 (1994-05-01), Rohrer et al.
patent: 5379231 (1995-01-01), Pillage et al.
patent: 6460165 (2002-10-01), Ismail et al.
patent: 6496960 (2002-12-01), Kashyap et al.
Baker & Botts L.L.P.
Paladini Albert W.
Silicon Graphics Inc.
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