Method and system for ensuring the assertion order of...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Reexamination Certificate

active

07102397

ABSTRACT:
Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.

REFERENCES:
patent: 6085342 (2000-07-01), Marholev et al.
patent: 6188256 (2001-02-01), Birns et al.
patent: 6744291 (2004-06-01), Payne et al.
patent: 2003/0038665 (2003-02-01), Naven

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