Method and system for ensuring interconnect integrity in a micro

Details Method and system for ensuring interconnect integrity in a micro Method and system for ensuring interconnect integrity in a micro

1992-11-17

1994-11-08

Wieder, Kenneth A.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

For fault location

324537, 324679, 324 731, G01R 3108

Patent

active

053630483

ABSTRACT:
The integrity of the interconnects in a predefined micro-chip-module are tested in two phases. Before any integrated circuit chips are loaded onto the micro-chip-module, the capacitance value of each interconnect is measured and the measured capacitance value is compared with a predetermined range of acceptable values to establish if an interconnect error exists. The measurement and comparison process is repeated after a predefined set of integrated circuit chips are loaded onto the micro-chip-module. The capacitance of each interconnect node is indicative of the total length of the interconnect traces of the node, and thus a short circuit will result in a capacitance measurement above the predetermined range for the node, and an open circuit will result in a capacitance measurement below the predetermined range for the node. In addition, the relationships between the capacitances of the nodes before and after loading the chips on the micro-chip-module can be represented by a set of equations, and those equations can be used to define the range of acceptable capacitance values for each node of the loaded micro-chip-module as a function of the capacitances of the input/outputs of the chips loaded onto the micro-chip-module.

REFERENCES:
patent: 3975680 (1976-08-01), Webb
patent: 4565966 (1986-01-01), Burr et al.
patent: 5138266 (1992-08-01), Stearns
patent: 5187430 (1993-02-01), Marek et al.

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