Method and system for enabling multiple store instruction comple

Details Method and system for enabling multiple store instruction comple Method and system for enabling multiple store instruction comple

1997-07-22

1999-07-20

Pan, Daniel H.

395564, 395582, 395391, G06F 906, G06F 9312, G06F 9305

Patent

active

059266457

ABSTRACT:
A method and system for a handling multiple store instruction completions in a processing system after a stall condition is disclosed. The processing system includes an instruction unit, the instruction unit including a dispatch unit and a completion unit, a translation unit and at least one execution unit. A load store unit comprises an instruction queue for receiving a plurality of instructions from the dispatch unit; at least one effective address (EA) unit for receiving the plurality of instructions from the instruction queue, and a store queue. The store queue is coupled to the translation unit, the at least one execution unit and the at least one EA unit. The store queue receives data and real address information relating to each of the plurality of instructions from the at least one execution unit prior to completion of each of the plurality of instructions. In so doing, the bottleneck associated with conventional systems, i.e., a maximum number of instructions that can be dispatched by the instruction unit is reduced.

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"Gathering Store Instructions In A Superscalar Processor," IBM Technical Disclosure Bulletin, vol. 39, No. 09, 103-105 (Sep. 1996).

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