Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-04-22
2001-04-24
Ngo, Ricky (Department: 2731)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C710S049000
Reexamination Certificate
active
06222846
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer system using input-output devices, and more particularly, to a computer system using an alternative prioritized interrupt dispatch procedure.
2. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be used as stand-alone workstations (high end individual personal computers) or linked together in a network by a “network server” which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (“E-mail”), document databases, video teleconferencing, whiteboarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (“LAN”) and wide area networks (“WAN”).
A significant part of the ever increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has, been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (“CPU”). The peripheral devices' data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the “Peripheral Component Interconnect” or “PCI.” A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; PCI BIOS Specification, revision 2.1, and Engineering Change Notice (“ECN”) entitled “Addition of ‘New Capabilities’ Structure,” dated May 20, 1996, the disclosures of which are hereby incorporated by reference. These PCI specifications and ECN are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
Computer system peripheral hardware devices, i.e., hard disks, CD-ROM readers, network interface cards, video graphics controllers, modems and the like, may be supplied by various hardware vendors. These hardware vendors must supply software drivers for their respective peripheral devices used in each computer system even though the peripheral device may plug into a standard PCI bus connector. The number of software drivers required for a peripheral device multiplies for each different computer and operating system. In addition, both the computer vendor, operating system vendor and software driver vendor must test and certify the many different combinations of peripheral devices and the respective software drivers used with the various computer and operating systems. Whenever a peripheral device or driver is changed or an operating system upgrade is made, re-testing and re-certification may be necessary.
The demand for peripheral device driver portability between operating systems and host computer systems, combined with increasing requirements for intelligent, distributed input-output (“I/O”) processing has led to the development of an “Intelligent I/O” (“I
2
O”) specification. The intelligent I/O architecture defines an environment for creating device drivers that are functionally divided between the host operating system and an intelligent I/O subsystem. The basic objective of the I
2
O specification is to provide an I/O device driver architecture that is independent of both the specific peripheral device being controlled and the host operating system. This is achieved by logically separating the portion of the driver that is responsible for managing the peripheral device from the specific implementation details for the operating system that it serves. By doing so, the part of the driver that manages the peripheral device becomes portable across different computer and operating systems. The I
2
O specification also generalizes the nature of communication between the host computer system and peripheral hardware, thus providing processor and bus technology independence. The I
2
O specification, entitled “Intelligent I/O (I
2
O) Architecture Specification,” Draft Revision 1.5, dated March 1997, is available from the I
2
O Special Interest Group, 404 Balboa Street, San Francisco, Cali. 94118; the disclosure of this I
2
O specification is hereby incorporated by reference.
The I
2
O operation is optimized for a single host node and a number of intelligent I/O subsystems. A host node is one or more application processors (typically, CPUs) and their resources executing a single homogeneous operating system. A typical host node utilizes a PENTIUM PRO multiprocessor manufactured by Intel Corp. running WINOWS NT, manufactured by Microsoft Corp. as the host operating system (OS).
FIG. 1
shows a typical hardware architecture for a computer system
100
, with a host node
101
and multiple embedded I/O processor nodes
131
and
141
. The host node
101
has one or more central processing units
102
(CPUs) operating on a local bus
108
that connects the CPUs
102
to the shared memory
104
and the system bridge
106
. The system bridge
106
connects the host node
101
to the input-output bus I/O. The input-output bus
110
is used to channel read and write messages to various I/O devices
160
,
162
,
164
and to the I/O processor nodes
131
and
141
. Pursuant to the I
2
O specification referenced above and incorporated by reference herein, a processor that is dedicated to I/O is called an embedded I/O processor node or an I/O platform (IOP). As shown in
FIG. 1
, a typical IOP
141
consists of a processor
142
, memory
144
, and I/O devices
150
and
152
all connected by a local I/O bus
148
. A system bridge
146
connects the IOP
141
to the input-output bus
110
. In operation, the IOP
141
handles I/O transactions between the host node
101
and the I/O devices
150
and
152
. Because the I/O devices
150
and
152
are not directly accessible to the host node
101
, these I/O devices are said to be hidden. Consequently, the drivers for these devices must execute on the IOP
141
, specifically on the CPU
142
. The IOP
141
and its private devices can be contained on typical add-in feature card, or the IOP
141
can have one or more expansion buses of its own.
IOPs need not have I/O devices attached within their own node. For example, IOP
131
has a CPU
132
, a local memory
134
connected by a local I/O bus
138
with a system bridge
136
connecting the local I/O bus
138
to the input/output bus
110
. In the latter instance, messages between the host node
101
and the I/O devices
160
,
162
and
164
can be processed by the CPU
132
of IOP
131
. Unlike the IOP
141
Bonola Thomas J.
Hammons Mark L.
Purcell Brian T.
Compaq Computer Corporation
Ngo Ricky
Williams Morgan & Amerson P.C.
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