Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
1998-11-12
2001-05-22
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S560000, C257S563000, C257S578000, C257S579000, C257S580000, C438S312000, C438S342000
Reexamination Certificate
active
06236072
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a vertical bipolar transistor and to a method of manufacturing a bipolar power transistor, said power transistors being primarily intended for high frequency applications, especially radio frequency applications.
STATE OF THE ART
Bipolar transistors for power amplification at high frequencies must, for a given supply voltage and operation frequency, fulfil a large number of detailed requirements concerning power amplification, ruggedness, breakdown voltage, noise, distortion, capacitance, input and output impedance, etc. The operation frequencies for modern telecommunications electronics vary from a few hundred MHz to several tens of GHz. Power transistors operate at high signal levels and high power densities where several components connected in parallel in a casing may be used.
The semiconductor material most frequently used for bipolar power transistors, at least at frequencies below 3 GHz, is silicon. A collector layer is epitaxially deposited on the substrate, and by subsequent, repetitive action of oxidation, lithography, etching, doping, deposition, etc., the transistor structure is formed. Also, because of the higher mobility of electrons compared to holes in silicon, primarily power transistors of npn type are used for the aforementioned application. The current flow through the transistor structure is normally vertical, with a higher doped subcollector region at the bottom of the structure. Metallic interconnecting layers are formed higher up in the structure.
With respect to
FIG. 1
, by varying the degree of doping in the collector
104
, the base terminals
101
and/or the emitter
102
, it is possible to obtain different types of frequency response and breakdown characteristics. Different lateral/vertical geometries give rise to transistors with different current capacities.
Amplifying RF signals poses several operation and design restraints on a power transistor. In order to maximize the current gain at high frequencies, the transistor must be able to handle a rather high collector current. The base current running from the base terminals
101
to the emitter region
102
causes a potential drop in the base region
103
laterally along the emitter region
102
. The forward bias of the emitter-base junction, V
be
(x) will therefore decrease towards the emitter center resulting in a crowding of the current density towards the emitter edges. This is demonstrated by the following formula:
I
c
=
I
o
(
ⅇ
v
be
(
x
)
kT
-
1
)
where I
c
is the collector current, I
0
is the base current, V
be
(x) is the laterally varying forward bias of the emitter-base junction, k is Boltman's constant, and T is temperature.
Current crowding is a common problem that occurs at higher current densities for bipolar transistors, which increases the peak current density at a given overall current.
FIG. 1
illustrates the current crowding effect through a principal cross section of a bipolar transistor through the emitter and base region. The dashed lines represent the base current and the solid lines represent the collector current.
FIG. 2
illustrates a principal collector diagram, showing the quasi-saturation region
210
where a high collector current causes the base-collector junction to become locally forward biased, due to the induced voltage drop in the neutral collector region. The effect, e.g., increases net charges stored in the base region, thereby introducing non-linearity in the transistor characteristics and a lowering of the cut-off frequency. Entering the quasi-saturation region results in a harmonic distortion at high frequencies, due to the non-linear characteristics of the transistor in this operating area.
Conventional silicon bipolar power transistors use ballast resistors to limit the current entering each emitter finger. This use of ballast resistors result in the need for a higher supply voltage in order to maintain the biasing to the linear region of the transistor operating area as illustrated in FIG.
2
. In addition, ballast resistors normally possess non-linear characteristics.
The following equation illustrates the relationship between f
T
, f
max
and two of the more relevant transistor parasitics, R
b
and C
bc
:
f
max
=
f
T
8
π
R
b
C
bc
where f
max
represents the maximum frequency for unity power gain of the transistor, f
T
is the frequency when the current gain of the transistor reaches unity, R
b
is the base resistance, and C
bc
is the capacitance of the base-collector junction. The base resistance, R
b
should be kept as low as possible since it affects the power gain at high frequencies. The base resistance is the resistance imposed on the base current during its path from the base contact to where the base current enters the emitter region.
The high current densities and output power of a conventional RF power transistor results in a temperature rise of the active chip area. The current gain of a conventional standard silicon bipolar transistor is thermally activated. At higher temperatures, the above situation becomes unstable and, if the current is not limited, destructive thermal runaway can occur. Using long emitter fingers or large area emitters results in a higher temperature rise in the center of the structure than close to the edges, since the heat dissipation is more limited at the center, thus further increasing the risk of thermal runaway. Since most conventional failure mechanisms are thermally activated, a high chip temperature should be avoided. Additionally, devices such as mobile telephones have limited cooling capabilities that add further constraints on the chip temperature.
As illustrated in
FIG. 3
, conventional silicon RF power transistors designed to handle large currents and high power levels are usually designed utilizing several emitter fingers of approximately 20-40 &mgr;m each. The whole transistor is then made up by connecting in parallel many transistor cells
310
. Using long and narrow emitter fingers
311
helps to reduce the path for the base current to traverse.
Emitter ballast resistors
312
limiting the current to each emitter finger
311
is the conventional way of dealing with thermal runaway for conventional silicon bipolar transistors. The emitter ballast resistors
312
are attached one to each emitter finger
311
. The emitter ballast resistors
312
are required to have a finite size that corresponds to the actual resistance value, thus limiting the number of emitter fingers
311
.
Using long and narrow emitter fingers also introduces additional problems since at high current densities, potential drops arise along the metal contacts of long emitter fingers contacting the emitter regions, thereby further enhancing the current density locally, according to
I
c
=
I
o
(
ⅇ
v
be
(
x
)
kT
-
1
)
as discussed above, i.e., the voltage drops decreases (V
be
) thus decreasing the collector current locally.
The increased temperature for each emitter requires the distribution of the transistor cells over a large area in order to manage the localized heating by increasing the heat dissipating area. The additional wiring necessary to connect all cells in parallel therefore contributes to the transistor parasitics.
SUMMARY OF THE INVENTION
The present invention provides a new structure for a power transistor using the SiGe process that addresses the aforementioned problems. The power transistor of the present invention is generally intended, but not limited to, a low power supply (e.g., less than or equal to 5V), RF application. In an exemplary embodiment of the present invention, a power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts.
The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitt
Brandt Per-Olof Magnus
Tilly Lars
Burns Doane Swecker & Mathis L.L.P.
Mintel William
Telefonaktiebolaget LM Ericsson (publ)
LandOfFree
Method and system for emitter partitioning for SiGe RF power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for emitter partitioning for SiGe RF power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for emitter partitioning for SiGe RF power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2472222