Method and system for efficient multiprocessor processing in...

Details Method and system for efficient multiprocessor processing in... Method and system for efficient multiprocessor processing in...

2008-07-08

2008-07-08

Nguyen, Van H (Department: 2194)

Electrical computers and digital processing systems: interprogra

Interprogram communication using message

Message using queue

C718S100000

Reexamination Certificate

active

10988062

ABSTRACT:
A multiprocessor system (206) having a plurality of processors (304-306), each processor capable of processing at least one queue (404A-404N) of at least one service application, and at least one task (402A-402N) comprising at least one of the at least one queue; and wherein a first processor and a second processor of the plurality of processors is each programmed to delegate (602) a service application from the first processor to a queue of the at least one queue of the second processor, evaluate (604-606) the queue at the second processor according to flow control criteria, process (608) the service application at the second processor upon satisfying the flow control criteria, and reject (610) the service application at the second processor upon failing to satisfy the flow control criteria.

REFERENCES:
patent: 5440741 (1995-08-01), Morales et al.
patent: 5574849 (1996-11-01), Sonnier et al.
patent: 5675807 (1997-10-01), Iswandhi et al.
patent: 5751932 (1998-05-01), Horst et al.
patent: 6157967 (2000-12-01), Horst et al.
patent: 6229813 (2001-05-01), Buchko et al.
patent: 6442565 (2002-08-01), Tyra et al.
patent: 6651111 (2003-11-01), Sherman et al.
patent: 6754321 (2004-06-01), Innes et al.
patent: 7032003 (2006-04-01), Shi et al.
patent: 7072354 (2006-07-01), Beathard
patent: 7209916 (2007-04-01), Seshadri et al.
patent: 2002/0194287 (2002-12-01), Tyra et al.
patent: 2004/0117459 (2004-06-01), Fry
patent: 2004/0125815 (2004-07-01), Shimazu et al.
patent: 2004/0192282 (2004-09-01), Vasudevan
patent: 2005/0102529 (2005-05-01), Buddhikot et al.
patent: 2005/0286457 (2005-12-01), Foster et al.
patent: 2005/0288001 (2005-12-01), Foster et al.
Tsuei et al. “Queuing Simulation Model for Multiprocessor Systems” 2003 IEEE, pp. 58-64.
Ayachi et al. “A Hierarchical Processor Scheduling Policy For Multiprocessor Systems” 1996 IEEE. pp. 100-109.
Allot Communications, “Multi-Level Traffic Management—White Paper”, P/N D004001 REV 1 A May 2000.

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