Method and system for efficient implementation of very large...

Details Method and system for efficient implementation of very large... Method and system for efficient implementation of very large...

2006-09-29

2009-10-06

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reexamination Certificate

active

07600098

ABSTRACT:
A method and system for efficient implementation of a large store buffer within a processor includes a store buffer within a processor having a first component configured to hold a plurality of younger stores requested by the processor and a second component configured to hold a plurality of older stores. The first component is implemented as a small content addressable memory (CAM) and the second component includes a first-in-first-out (FIFO) buffer to hold the data and addresses of the plurality of older stores and an address disambiguator to hold the addresses of each of the plurality of older stores found in the FIFO buffer. The processor uses the small CAM to perform most of the store-to-load forwarding in a fast and efficient way thereby enhancing processor performance.

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Stone, Sam S., Woley, Kevin M., Frank, Matthew I. “Address-indexing memory disambiguation and store-to-load forwarding” Proceedings of the 38thannual IEEE/ACM international symposium of microarchitecture, Nov. 2005.

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