Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-02-16
2003-06-10
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S226000
Reexamination Certificate
active
06577535
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to voltage generation and, more particularly, to voltage generation internal to memory systems.
2. Description of the Related Art
Memory cards are commonly used to store digital data for use with various products (e.g., electronics products). Examples of memory cards are flash cards that use Flash type or EEPROM type memory cells to store the data. Flash cards have a relatively small form factor and have been used to store digital data for products such as cameras, hand-held computers, set-top boxes, hand-held or other small audio players/recorders (e.g., MP3 devices), and medical monitors. A major supplier of flash cards is SanDisk Corporation of Sunnyvale, Calif.
FIG. 1
is a block diagram of a conventional memory system
100
. The conventional memory system
100
represents, for example, a memory card (e.g., flash card). The conventional memory system
100
includes a memory controller
102
and memory chips
104
-
110
. The number of memory chips
104
-
110
is dependent upon the storage capacity to be provided by the conventional memory system
100
. The memory controller
102
receives an input voltage (V
IN
)
112
and an Input/Output (I/O) bus
114
. The memory controller
102
operates to supply an address/data/control bus
116
to each of the memory chips
104
-
110
. In addition, the memory controller
102
produces a chip select (CS) signals
118
that is provided to chip enable (CE) terminals of each of the memory chips
104
-
110
. The memory controller
102
uses the chip select signals
118
to selectively activate one of the memory chips
104
-
110
that is to be accessed for data storage or retrieval. In addition, since the memory chips
104
-
110
require various voltage levels for operation, the memory controller
102
includes a charge pump and regulation circuit
120
. The charge pump and regulation circuit
120
is centrally provided in the memory controller
102
and produces several different output voltage levels that are supplied to each of the memory chips
104
-
110
over a voltage supply
122
. As an example, the input voltage (V
IN
)
112
might be 3.3 or 1.8 Volts and the different output voltage levels might be 3 Volts, 6 Volts, 12 Volts and 24 Volts.
Although the memory system
100
shown in
FIG. 1
is suitable for high speed and high capacity usage, there have been problems in fabricating the memory controller
102
of the memory system
100
. In particular, there exists only a limited number of semiconductor fabrication foundries that are able to and desirous of fabricating the memory controller
102
with the charge pump and regulator
120
incorporated therein. The charge pump and regulator circuit
120
requires high voltage devices and thus a more sophisticated fabrication process is required when fabricating the memory controller
102
. Given the limited availability of foundries for fabricating the memory controller
102
, it is desired to find alternative ways to produce a memory system that operates with high speed and high capacity yet avoids the need for sophisticated processing of the memory controller
102
so that more fabrication foundries are available.
One solution is to remove the charge pump and regulator
120
from the memory controller
102
. This results in the memory controller
102
being substantially easier to fabricate and thus opens its fabrication up to numerous available foundries. The charge pump and regulator circuitry therefore need to be provided elsewhere within the memory system. In one approach, the charge pump and regulator circuitry can be provided within each memory chip. However, providing charge pump and regulator circuitry within the memory chips is not burdensome because the memory chip is already a sophisticated integrated circuit device that utilizes a sophisticated processing, particularly non-volatile (e.g., FLASH) memories. However, during operation, a problem results from the noise generated by the high voltage devices within the charge pump and regulator circuit. As a result, delicate analog circuitry within the memory chips is disturbed by this noise and therefore causes the performance of the memory chip to be slowed in order to compensate for the added noise.
Thus, there is a need for improved approaches for including charge pump and regulator circuitry within memory systems which do not limit foundry availability and which do not compromise performance.
SUMMARY OF THE INVENTION
Broadly speaking, the invention relates to techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) and a controller chip. The various voltage levels can be produced by charge pump and regulator circuitry within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. The memory system is suitable for high performance operation and foundry availability for controller fabrication is not hindered by the presence of voltage (supply) generation circuitry.
The invention can be implemented in numerous ways including, a system, device, or method. Several embodiments of the invention are discussed below.
As a memory system for storing data, one embodiment of the invention includes at least: a memory controller; a plurality of memory blocks operatively connected to the memory controller, each of the memory blocks including at least data storage elements and a voltage generation system; and a power bus operatively connected to the charge pump circuit for each of the memory blocks. During operating of the memory system, when one of the memory blocks is activated, the voltage generation system circuit within the one of the memory blocks is deactivated and instead another of the voltage generation system associated with another of the memory blocks is activated to supply different voltage level signals to the one of the memory blocks via the power bus. As a memory system, another embodiment of the invention includes at least: a first memory block including at least first data storage elements and a first charge pump circuit; a second memory block including at least second data storage elements and a second charge pump circuit; a memory controller operatively connected to the first memory block and the second memory block, the memory controller producing at least one select signal, the at least one select signal being used in selective activation of the first and second memory blocks; and a power bus operatively connecting the first charge pump circuit and the second charge pump circuit.
As a method for power generation within a memory system having a plurality of memory blocks, with each of the memory blocks including a power generation circuit, one embodiment of the invention includes at least the acts of: activating one of the memory blocks for data access while the other of the memory blocks are deactivated; activating one of the power generation circuits residing in one of the memory blocks that is deactivated; and supplying power from the one of the power generation circuits that is activated to the one of the memory blocks that is activated.
As a memory chip, one embodiment of the invention includes at least: a plurality of data storage elements for storage of data; and a power generation circuit for generating power signals. The memory chip includes a chip enable for enable/disable of the data storage elements of the memory chip, and the memory chip includes a charge pump enable for enable/disable of the power generation circuit.
As a memory system, another embodiment of the invention includes at least: a first memory block means for storing data in first data storage elements and for producing first power signals; a second memory block means for storing data in second data storage elements and for producing second power signals; a memory controller operatively connected to the first memory block means and the second memory block means, the memory controller producing at least one select signal, the at least one
Beyer Weaver & Thomas LLP
Lebentritt Michael S.
Phung Anh
SanDisk Corporation
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