Multiplex communications – Fault recovery
Reexamination Certificate
2000-05-18
2004-06-22
Kizou, Hassan (Department: 2662)
Multiplex communications
Fault recovery
C370S360000, C714S012000, C714S731000
Reexamination Certificate
active
06754171
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to packet switched communications networks and more particularly to the distribution of a clock within a packet switched network device.
BACKGROUND OF THE INVENTION
Circuit switched digital telecommunications networks are end-to-end synchronized communications system that are ideal for carrying voice conversations. Clocking signals utilized to synchronize circuit switched networks are typically generated in a central location and are then distributed to various switching hardware throughout the network.
Because the integrity of the network depends on synchronized clocking, it is important that the clock distribution mechanism can recover from a failure in the master clock distribution system. Specifically, in order to prevent degradation of voice conversations, a failed clock signal should be recovered in less than 50 microseconds. One technique for recovering from a failed clock in a circuit switched telecommunications network is disclosed in U.S. Pat. No. 5,870,441 issued to Cotton et al.
In contrast to circuit switched digital telecommunications networks, packet switched networks do not provide end-to-end synchronized connections between users and are therefore not as adapt at carrying voice conversations. In an effort to emulate the voice carrying capability of circuit switched networks and to maximize the bandwidth of packet switched networks, it is desirable to provide synchronized connections between network nodes in a packet switched network. For example, in an optical network utilizing asynchronous transfer mode (ATM) over synchronous optical network (SONET)/synchronous digital hierarchy (SDH) it is desirable to be able to receive a signal on an input port of a network switch and to transmit a synchronized version of the signal from an output port of the same switch.
Providing synchronized transmissions in packet switched networks typically involves recovering the clock from a selected incoming signal and distributing the recovered clock to target ports of a network switch. The recovered clock is then utilized by output ports on the switch to transmit synchronized signals to other network switches. While the distribution of a synchronized clock throughout a packet switched network works well to emulate a circuit switched network, the clock timing of the packet switched network is subject to a single point of failure. That is, if the transmission link carrying the source clock fails then the ports in the network that are relying on the source clock will not have a clock to transmit signals.
As with circuit switched networks, it is important that packet switched networks can quickly recover from a failure of a distributed source clock. Although a circuit switched network carrying primarily voice conversations can withstand up to 50 microseconds of interruption due to a clock failure, a high bandwidth packet switched network will suffer a large volume of dropped packets during a clock failure that lasts up to 50 microseconds. In order to minimize the volume of packets that are dropped as a result of a distributed clock failure, it is desirable to overcome clock failures in as short of time as possible.
In view of the push towards making high bandwidth packet switched networks emulate circuit switched networks and in view of the large volume of packets that are lost when a distributed clock in a packet switched network fails, what is needed is a technique for providing protection from a distributed clock failure in a packet switched network.
SUMMARY OF THE INVENTION
A system and method for providing protection from a distributed clock failure in a packet switched network device involves monitoring primary clocking information that is received from an input port of the network device, distributing the clocking information to an output port for use in synchronous transmissions, and supplying backup clocking information from within the packet switched network device to the output port if the primary clocking information fails. In an embodiment, the integrity of the primary clocking information is directly monitored in hardware and the backup clocking information is provided by a local clock source that is located within the network device. If a failure in the primary clocking information is detected, the backup clocking information is supplied to the output port from the local clock source. Because the integrity of the primary clocking information is monitored in hardware and because the clock switching is hardware triggered, a clock failure can be identified and corrected in a relatively short period of time, thereby minimizing packet loss during clock failures.
In an embodiment, the hardware based failure protection mechanism provides failure protection on a single switch module. In an embodiment, a switch module includes a first input port for receiving flows of packets and a primary clock, a fault monitoring system within the switch module for detecting a failure of the primary clock, a first output port for transmitting flows of packets, circuitry for distributing the primary clock from the first input port to the first output port, a transmitter that utilizes the primary clock for transmitting packets from the first output port in synchronization with the primary clock, a secondary clock source that provides a secondary clock within the switch module, and circuitry for supplying the secondary clock to the first output port upon detection of a failure of the primary clock by the fault monitoring system. In an embodiment, the secondary clock is a local clock source that resides within the switch module.
In an embodiment, the hardware based failure protection mechanism provides failure protection to a network device that includes multiple switch modules. The network device includes a first switch module located within the network device with the first switch module including a first input port for receiving flows of packets and a primary clock, circuitry for distributing the primary clock from the first input port to other output ports on other switch modules within the network device, and a second switch module located within the network device having a first output port for transmitting packets in synchronization with the primary clock. The hardware based failure protection mechanism also includes circuitry for providing a secondary clock, a link fault monitor for detecting a failure of the primary clock, and circuitry for supplying the secondary clock to the first output port upon detection of a failure of the primary clock. In an embodiment, the secondary clock is a local clock source that resides within the second switch module.
In an embodiment, a firmware based failure protection mechanism involves programming a firmware control unit to provide a specified clock as a secondary clock in case of a failure of the primary clock. In an embodiment, the secondary clock is obtained from a second input port and not from a local clock source. The firmware control unit can be programmed to provide the secondary clock from various sources and therefore provides a more customized and permanent solution to failure protection than the hardware based mechanisms.
In an embodiment, a clock failure protection method includes steps of receiving flows of packets and a primary clock at a first input port of a packet switched network device, monitoring the primary clock, within the packet switched network device, for a clock failure, distributing the primary clock to a first output port of the packet switched network device, transmitting packets from the first output port in synchronization with the primary clock, and supplying the first output port with a local clock source from within the network device for the transmission of packets when the monitoring of the primary clock indicates a clock failure.
In an embodiment of the method, the step of monitoring includes utilizing a field programmable gate array located within the packet switched network device to determine if the primary clock has failed. In an embodiment of the method, the step
Bernier Daniel J.
Edin Deborah E.
Kenly Stewart G.
Enterasys Networks Inc.
Kizou Hassan
Levitan D
Wilson Mark A.
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