Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2002-04-12
2004-05-18
Le, N. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S537000, C324S763010, C324S765010
Reexamination Certificate
active
06737876
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method and system for determining the operating voltage for a semiconductor device.
BACKGROUND OF THE INVENTION
FIG. 1
depicts a conventional semiconductor device
10
. The semiconductor device
10
includes active areas
11
and
12
where devices, such as memory cells and/or logic, are formed. Across the active areas
11
and
12
are conductive lines
14
and
16
. The conductive lines
14
and
16
are preferably polysilicon lines. The semiconductor device
10
also conventional silicon trench isolation (“STI”) structures
18
between the active areas
11
and
12
. The STI isolation structures
18
are used to isolate different portions of a semiconductor device. Although only some of the conventional STI structures
18
are marked, there are additional conventional STI structures. Furthermore, the conventional semiconductor device
10
typically includes other devices (not shown).
FIG. 2
depicts a device
20
formed in the conventional semiconductor device
10
. The conventional semiconductor device
10
could include other devices, such as, memory cells. The device
20
includes a gate
22
having spacers
24
and
26
. The spacers
24
and
26
are typically between five hundred and one thousand Angstroms in thickness. The gate
22
is separated from the underlying substrate
21
using oxide
23
. The device
20
also includes a source
30
and a drain
34
. The source
30
also includes a source extension
34
that is under the gate
22
. Similarly, the drain
32
includes a drain extension
36
that is under the gate
22
. The source extension
34
and the drain extension
36
are typically between eighty and one hundred Angstroms in thickness. Also depicted are conventional STI structures
40
and
42
that isolate the device
20
from other portions of the semiconductor device
10
.
In order to operate the conventional semiconductor device
10
, an operating voltage must be selected. In order to choose the operating voltage, the maximum operating voltage allowed to be used with the conventional semiconductor device
10
is selected. In order to do so, the lifetime of the conventional semiconductor device is determined. Typically the lifetime is determined using a time dependent dielectric breakdown (“TDDB”) test and/or a voltage ramp dielectric breakdown (“VRDB”) test on a particular conventional semiconductor device
10
. The TDDB test applies a particular voltage to the conventional semiconductor device
10
until the conventional semiconductor device
10
fails. The VRDB test applies an increasing voltage, typically one that increases in steps, to the conventional semiconductor device
10
until the conventional semiconductor device
10
fails. Thus, the lifetime of the conventional semiconductor device
10
, including the dependence of the lifetime on the operating voltage, can be determined.
Based on the lifetime experimentally determined and the desired lifetime for the semiconductor device
10
, the maximum operating voltage of the conventional semiconductor device
10
is determined. During operation, an operating voltage that is less than or equal to the maximum operating voltage is utilized. As a result, the conventional semiconductor device
10
should last for the desired amount of time. For example, it is typically desired to have a lifetime of ten years during use. The operating voltage used and the maximum operating voltage allowed to be used with the conventional semiconductor device
10
are set so that the lifetime of the conventional semiconductor device
10
is as desired.
Although the conventional semiconductor device
10
functions, one of ordinary skill in the art will readily realize that the polysilicon lines
14
,
16
and
22
affect the lifetime at a particular operating voltage. In particular, the source extension
34
and the drain extension
36
can result in a weaker oxide
23
. In addition, the areas of the source extension
34
and the drain extension
36
are sites for a low voltage leakage current, even for the off state of the device
20
. Moreover, the effect of the leakage current increases as the length of the channel is decreased when the gate
22
is made less wide. Thus, as the conventional semiconductor device is scaled down to allow for a higher density of devices
20
, problems due to leakage current, as well as problems with the quality of the oxide
23
, increase. Consequently, it would be desirable to account for the overlap between the gate
22
and the source
30
and drain
34
in the area of the source extension
34
and the drain extension
36
could be accounted for.
Furthermore, the STI structures
18
,
40
and
42
can reduce the lifetime of the device.
FIG. 2B
depicts a conventional STI structure
42
. However, the other conventional STI structures in the conventional semiconductor device
10
may suffer from the same defects. The conventional STI structure
42
includes conventional trench
44
, which is filled with conventional oxide filler
46
. Near the corners of the conventional STI structure
42
, the oxide filler
46
has thinned in areas
48
and
50
. The thinned areas
48
and
50
reduce the ability of the STI structures
18
,
40
and
42
to insulate the devices
20
. As a result, a leakage current can occur through the thinned areas
18
,
40
and
42
. The leakage current can lower the threshold voltage of devices fabricated near the conventional STI structures
18
,
40
and
42
, which adversely affect performance of the conventional semiconductor device
10
.
The thinned areas
48
and
50
may occur for a variety of reasons. Typically, silicon wafers having a (
100
) orientation (shown in
FIG. 2B
) are used for fabricating conventional semiconductor devices
10
. Because the top surface has a (
100
) orientation, near the corners of the trenches
48
and
50
, the exposed silicon has a (
111
) orientation. The (
111
) orientation of silicon has a larger number of dangling bonds. Thus, when the oxide filler
46
is provided, areas near the (
111
) orientation are thinner. In addition, mechanical stress tends to concentrate at areas where a corner is fabricated. Mechanical stress also tends to cause a thinning of the oxide filler
46
near the corners of the conventional STI structures
18
,
40
and
42
. In addition, as discussed above, in more recent conventional Flash memory devices, a nitride oxide, such as N
2
O is used in forming the gate oxide for the memory cells in the core region. When N
2
O is used, the thinning that results in the areas
48
and
50
is even more severe. Thus, the problems due to leakage current in the semiconductor device
10
are made worse.
Accordingly, what is needed is a system and method for determining the operating voltage of the semiconductor device that takes into account the overlap between the source and/or drain extensions and the polysilicon lines as well as the STI structures. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for determining an operating voltage for a semiconductor device. The semiconductor device includes at least one active area, at least one silicon trench isolation (STI) structure and a plurality of polysilicon lines. The method and system comprise determining a first plurality of lifetimes and a second plurality of lifetimes. The first plurality of lifetimes is determined for a first plurality of semiconductor devices having a first plurality of polysilicon lines, at least a first active area and a first plurality of STI structures for separating the at least the first active area. The first plurality of polysilicon lines has a particular area and a plurality of peripheral lengths. Each of the first plurality of STI structures has a length. The second plurality of lifetimes is determined for a second plurality of semiconductor devices having a second plurality of polysilicon lines, at least a second active area and a second plurality of STI str
Advanced Micro Devices , Inc.
Le N.
Teresinski John
Winstead Sechrest & Minick P.C.
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