Method and system for determining an interconnect delay...

Details Method and system for determining an interconnect delay... Method and system for determining an interconnect delay...

2005-11-22

2005-11-22

Homere, Jean R. (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C703S002000, C703S013000, C716S030000, C716S030000

Reexamination Certificate

active

06968306

ABSTRACT:
A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Ceffis computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Ceffis characterized by:in-line-formulae description="In-line Formulae" end="lead"?Ceff=Cfj(1−e−T/τdj)in-line-formulae description="In-line Formulae" end="tail"?where Cfjis the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and τdj is the resistance of the pi-model (Rdj) multiplied by Cfj. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.

REFERENCES:
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