Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1999-01-14
2004-08-24
Fan, Chieh M. (Department: 2634)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C375S357000, C370S510000, C370S523000
Reexamination Certificate
active
06782066
ABSTRACT:
FIELD OF INVENTION
This invention generally relates to techniques for data communication over an all-digital communication channel. More specifically, it relates to a method and system for detecting frame slips in a digital end-to-end communication channel.
BACKGROUND OF THE INVENTION
Timing synchronization is critical for digital data transmission. For example, a typical T1 digital communication system time-division multiplexes 24 digitally encoded DS-0 voice channels to form a DS-1 digital signal. Each of the DS-0 communication channels carries an 8-bit code word formed by sampling a signal at an 8000 times per second rate (8 KHz), resulting in a 64 Kbps communication channel. Together, the 24 time-division multiplexed (“TDM”) 64 Kbps communication channels form a 1.544 Mbps DS-1 signal. A DS-1 frame thus includes 24 multiplexed or interleaved 8-bit code words or octets. In addition, a framing bit is added to form a 193-bit (24×8+1) frame. The DS-1 frame of 193 bits repeats 8000 times per second to form the T1 1.544 Mbps line rate (193×8000=1,544,000).
To properly receive the DS-1 frame, a receiver must be precisely synchronized with the transmitter to detect the beginning and end of the DS-1 frame, and allow identification of the 24 individual TDM channels. Because the DS-1 frame is only 125 microseconds in duration, a loss of synchronization will cause an alignment slip that may result in data being lost. To detect the frame synchronization, the framing bit may be alternated between 1 and 0 to establish an identifiable frame synchronization bit pattern. The alternating 1, 0, 1, 0, 1, 0 framing sequence is a uniquely identifiable framing bit pattern that does not appear in ordinary voice traffic.
Loss of synchronization typically occurs between a transmitter and a receiver using clock frequency sources that cannot always be precisely synchronized. Despite attempts to synchronize the clocks of the communicating devices, the clock rates between two devices will inevitably not be exactly the same. Communication devices often use elastic stores to reconcile differences in clock rates from different sources. Eventually, however, the offset between the clocks of the devices may build up or accumulate until the elastic stores can no longer reconcile the differences. One problem caused by a loss of synchronization is a periodic frame slip, where a complete frame of data is either repeated or lost depending on the relative skew of the transmitting and receiving clocks. The elastic buffers gradually fill (or empty) until it either overflows (or underflows) and a slip occurs. Such frame slips may be difficult to detect and correct because there is no mechanism to detect a repetition or loss of an entire frame of data, especially at the DS-0 signal level. Because such losses in synchronization may occur, techniques for detecting and correcting such communication errors are necessary.
Certain other digital interface protocols, such as the Integrated Services Digital Network (“ISDN) protocol, provide additional overhead bits for synchronizing data transmission. ISDN uses High Data Link Control (“HDLC”) framing which provides a specific data pattern or “flag” to indicate the end of data blocks and detect any frame slips. To ensure the data pattern uniquely identifies the end of a data block, the transmitters are prohibited from transmitting the specific data pattern as part of a data sequence by using an appropriate bit insertion algorithm. HDLC framing, however, requires headers, sequence numbers and error correction overhead bits that consume communication data bandwidth.
When transmitting digital data at high data rates over a digital communication channel through the Public or General Switched Telephone Network (“GSTN”), such as with the proposed V.90 all-digital mode (56 Kbps) or V.91, additional overhead bits may not be available for frame synchronization. In the V.90 all-digital mode, two communication devices are communicating through the PSTN via an all-digital connection using baseband PCM codes. As part of a communication training sequence, the two devices determine exactly which PCM codes can be used for data transfer, and which cannot be used due to impairments in the digital network such as digital pads, robbed bits, sign bit inversion, zero byte suppression, A-Law to u-law transcoding, etc. Once these channel impairments are determined and the appropriate PCM codes are selected, the primary event in the network that will cause data communication errors is frame slip due to loss of synchronization. In achieving the highest bit rates, however, all available bits are used for data transfer, leaving no overhead bits to detect frame synchronization. Needed is a mechanism for providing synchronization and detecting loss of fame during high-speed data transmission over all-digital communication lines through the GSTN that consumes a minimum amount of available communication bandwidth.
SUMMARY OF THE INVENTION
In accordance with an illustrative embodiment of the present invention, the problems associated with the synchronization of frames of data and detecting loss of frame synchronization in a digital communication channel are addressed. The present embodiment provides a method and device for detecting frame or digital slips due to loss of synchronization in a digital communication channel.
In an illustrative embodiment according to an aspect of the invention, a method of transmitting data to detect frame slips in a digital communication channel is described. The method includes stealing a number of data bits in a transmitted digital signal for use as a control channel to monitor synchronization of the communication channel. For example, the sign bits of each of the octets of a particular data frame are robbed and used as a control channel for timing synchronization of the transmitted data. In an illustrative example, the particular data frame may be selected periodically such as 1 of N number of data frames, where N may be equal to every 1600 frames. There are 6 octets in a data frame and the sign bits of each octet of the particular frame can be set to a unique synchronization bit pattern that is not likely to occur in transmitted data.
To detect a frame slip, the receiver monitors the control channel for the unique bit pattern. If the unique bit pattern is not detected in the expected periodic frame, a synchronization problem has occurred between the transmitter and the receiver and it can be assumed that a frame slip has occurred. For example, if a frame slip has occurred, the control channel bits will be detected out of their normally expected sequence or positions, such as the synchronization bit pattern being detected one octet too early or late. In either case, data bits will be detected in bit positions where the control channel frame should be and the unique bit pattern of the synchronization bit pattern of the control channel will not be matched, thus indicating a frame slip. The synchronization bit pattern should therefore be chosen such that it can be detected and distinguished from a data bit pattern after a frame slip. In a particular example, all logic 1s or a pair of logic 0's framing a series of logic 1s, 01111110 can be utilized.
In other embodiments, the control channel may also be used to carry other information such as a clear down of the call or a request to retrain. The control channel may also be used to carry other types of data.
In an embodiment of the invention, a transmitter can be embodied as including a counter maintaining a count of frames of data, a buffer for storing a bit pattern, and a multiplexer for inserting the bit pattern.
According to another aspect of the invention, executable software code and a computer system with memory is used to implement the described embodiment. Alternatively, dedicated hardware, discrete logic, programmable logic devices (“PLD”), application specific integrated circuits (“ASIC”) may be used to implement the described embodiment. In an illustrative embodiment, a counter, a buffer or r
Nicholas Michael G.
Parizhsky Vladimir G.
3Com Corporation
Fan Chieh M.
McDonnell & Boehnen Hulbert & Berghoff
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