Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2003-03-10
2004-07-20
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S200000, C365S201000
Reexamination Certificate
active
06765827
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flash memory devices, and more particularly, to a method and system for detecting defective material surrounding flash memory cells of a flash memory device.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a flash memory cell
100
of a flash memory device includes a tunnel dielectric structure
102
typically comprised of silicon dioxide (SiO
2
) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure
102
is disposed on a P-well
103
formed within a semiconductor substrate
105
. In addition, a floating gate structure
104
, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure
102
.
In addition, a floating dielectric structure
106
, typically comprised of silicon dioxide (SiO
2
), is disposed over the floating gate structure
104
. A control gate structure
108
, comprised of a conductive material, is disposed over the dielectric structure
106
. The tunnel dielectric structure
102
, the floating gate structure
104
, the floating dielectric structure
106
, and the control gate structure
108
form a gate stack of the flash memory cell
100
.
A drain bit line junction
110
is formed toward the left of the gate stack of the flash memory cell
100
within an active device area of the P-well
103
defined by STI (shallow trench isolation) structures
107
. Similarly, a source bit line junction
114
is formed toward the right of the gate stack of the flash memory cell
100
within the active area of the P-well
103
. When the P-well
103
is doped with a P-type dopant, the drain and source bit line junctions
110
and
114
are doped with an N-type dopant, such as arsenic (As) or phosphorous (P) for example, for forming an N-channel flash memory cell
100
. Such a structure of the flash memory cell
100
is known to one of ordinary skill in the art of flash memory technology.
During the program or erase operations of the flash memory cell
100
of
FIG. 1
, charge carriers are injected into or tunneled out of the floating gate structure
104
. Such variation of the amount of charge carriers within the floating gate structure
104
alters the threshold voltage of the flash memory cell
100
, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure
104
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure
104
, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
FIG. 2
illustrates a circuit diagram representation of the flash memory cell
100
of
FIG. 1
including a control gate terminal
150
coupled to the control gate structure
108
, a drain terminal
152
coupled to the drain bit line junction
110
, a source terminal
154
coupled to the source bit line junction
114
, and a P-well terminal
156
coupled to the P-well
103
.
FIG. 3
illustrates a flash memory device
200
comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to
FIG. 3
, the array of flash memory cells
200
includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell
100
of
FIGS. 1 and 2
. The array of flash memory cells
200
of
FIG. 3
is illustrated with
2
columns and
2
rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to
FIG. 3
, in the array of flash memory cells
200
comprising an flash memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In
FIG. 3
, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line
202
, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line
204
.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In
FIG. 3
, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line
206
, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line
208
. Further referring to
FIG. 3
, the source terminal of all flash memory cells of the array
200
are coupled together to a source voltage V
SS
, and the P-well terminal of all flash memory cells of the array
200
are coupled together to a substrate voltage V
SUB
during some modes of operation of the flash memory cell. Such a circuit of the array of flash memory cells comprising the flash memory device
200
is known to one of ordinary skill in the art of flash memory technology.
Referring to
FIG. 4
, an inter-level dielectric material
120
surrounds the gate stack of the flash memory cell
100
. The inter-level dielectric material
120
may be comprised of silicon dioxide (SiO
2
) or a low-k dielectric material having a dielectric constant lower than that of silicon dioxide (SiO
2
). Such an inter-level dielectric material
120
is known to one of ordinary skill in the art of integrated circuit fabrication.
Further referring to
FIG. 4
, during operation of the flash memory cell
100
within a flash memory device
200
, a high voltage difference, such as a voltage difference of about 15 Volts for example, may be repeatedly applied between the control gate
108
and the drain or source bit line junctions
110
and
114
. If the inter-level dielectric material
120
is defective, such repeated application of the high voltage difference between the control gate
108
and the drain or source bit line junctions
110
and
114
may result in break-down of the inter-level dielectric material
120
. With such break-down of the inter-level dielectric material
120
, a short-circuit may be formed through the inter-level dielectric material
120
between the control gate
108
and the drain or source bit line junctions
110
and
114
(as illustrated by the dashed line
122
in FIG.
4
).
Such a short-circuit between the control gate
108
and the drain or source bit line junctions
110
and
114
renders the flash memory cell
100
and thus the flash memory device
200
having the flash memory cell
100
inoperative. Thus, a mechanism is desired for detecting for defective dielectric material surrounding the flash memory cells of a flash memory device.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a stressing voltage is applied between the control gate and a well of the flash memory cell during testing for breaking down any defective dielectric material surrounding the flash memory cell such that the defective dielectric material may be detected during testing.
In one embodiment of the present invention, in a method and system for detecting defective material surrounding a flash memory cell, a stressing voltage is applied between a control gate and a well of the flash memory cell. A stress recovery process is then performed on the flash memory cell. Any short circuit, formed through the defective material between the control gate and at least one of drain and source bit line junctions of the flash memory cell, is detected.
In one embodiment of the present invention, the material surrounding the flash memory cell is an inter-level dielectric material. In another embodiment of the present invention, the flash memory cell is an N-channel flash memory cell. In that cas
Kwan Ming
Li Jiang
Choi Monica H.
Lam David
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