Method and system for detecting bypass error conditions in a loa

Details Method and system for detecting bypass error conditions in a loa Method and system for detecting bypass error conditions in a loa

1996-01-18

1998-05-12

Beausoliel, Jr., Robert W.

39518504, G06F 1128

Patent

active

057519463

ABSTRACT:
A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary of the load instruction and a real address to a word boundary of the executing store instruction match, and identifying a bypass error condition for the load instruction when the load instruction has executed out-of-order with respect to the executing store instruction. In a system aspect, the system includes a load queue, detection logic, and completion logic. The load queue includes a real page number buffer for storing a real address to a word boundary for each executed load instruction. The detection logic compares real addresses to a word boundary for a load instruction against an executing store instruction and compares a program order of the load instruction and the executing store instruction when the real addresses to a word boundary match. The completion logic receives the executing store instruction and a bypass error signal when the load instruction has executed out-of-order with respect to the executing store instruction. The completion logic also receives the identifier of the load instruction which bypassed the executing store instruction.

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