Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
1999-11-04
2003-04-15
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C714S038110
Reexamination Certificate
active
06550002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved data processing system and, in particular, to a method and system for monitoring instruction execution within a processor in a data processing system.
2. Description of Related Art
In typical computer systems utilizing processors, system developers desire optimization of software execution for more effective system design. Usually, studies are performed to determine system efficiency in a program's access patterns to memory and interaction with a system's memory hierarchy. Understanding the memory hierarchy behavior helps in developing algorithms that schedule and/or partition tasks, as well as distribute and structure data for optimizing the system.
Within state-of-the-art processors, facilities are often provided which enable the processor to count occurrences of software-selectable events and to time the execution of processes within an associated data processing system. These facilities are known as the performance monitor of the processor. Performance monitoring is often used to optimize the use of software in a system. A performance monitor is generally regarded as a facility incorporated into a processor to monitor selected characteristics to assist in the debugging and analyzing of systems by determining a machine's state at a particular point in time. Often, the performance monitor produces information relating to the utilization of a processor's instruction execution and storage control. For example, the performance monitor can be utilized to provide information regarding the amount of time that has passed between events in a processing system. As another example, software engineers may utilize timing data from the performance monitor to optimize programs by relocating branch instructions and memory accesses. In addition, the performance monitor may be utilized to gather data about the access times to the data processing system's L1 cache, L2 cache, and main memory. Utilizing this data, system designers may identify performance bottlenecks specific to particular software or hardware environments. The information produced usually guides system designers toward ways of enhancing performance of a given system or of developing improvements in the design of a new system.
Events within the data processing system are counted by one or more counters within the performance monitor. The operation of such counters is managed by control registers, which are comprised of a plurality of bit fields. In general, both control registers and the counters are readable and writable by software. Thus, by writing values to the control register, a user may select the events within the data processing system to be monitored and specify the conditions under which the counters are enabled.
To evaluate the efficiency of a processor, it is necessary to determine how much work is performed and how many resources are consumed on behalf of executing instructions. Many modern processors implement speculative processing to achieve high performance. As a result, some of the instructions that are processed may be canceled or flushed without completely executing because the condition for which they were speculatively executed did not occur. Like any other instruction, speculative instructions consume resources within the processor.
Most modern processors implement performance monitor counters that count the occurrence of predefined events associated with the use of resources. However, in a processor with both performance monitoring and speculative execution of instructions, performance monitor counters count events for both non-speculative instructions, i.e. instructions which complete execution, and speculative instructions, i.e. instructions which do not complete. Time is a critical resource within a processor, and as with most operations within a processor, instruction flushing is completed as quickly as possibly. Hence, it is not desirable at the time that instructions are flushed to inspect, flag, and/or count which instructions are being flushed.
Therefore, it would be advantageous to have a method and system for monitoring the use of resources accurately within a processor that performs speculative execution of instructions. It would be further advantageous to have a method and system monitoring the flushing of particular instructions without slowing the flushing functionality.
SUMMARY OF THE INVENTION
A method and system for detecting flushed instructions without a flush indicator is provided. In order to monitor the flushing of an instruction in an instruction pipeline of a processor, an instruction is selected as a sampled instruction and the progress of the sampled instruction through the instruction pipeline is monitored. Upon selection of an instruction as a sampled instruction, a countdown value is initialized to a value equal to the maximum number of instructions within the instruction pipeline, and as instructions complete, the countdown value is decremented. If progress of the sampled instruction is detected as the instruction moves through the instruction pipeline, the countdown value is reinitialized. If the countdown value reaches zero, then a flush of the sampled instruction from the instruction pipeline is presumed, and an indication that the sampled instruction has been flushed is generated. In response to the indication that the sampled instruction has been flushed, a subsequent instruction may be selected as a subsequently sampled instruction.
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Davidson Joel Roger
Le Hung Oui
Mericas Alexander Erik
Coleman Eric
McBurney Mark E.
Nichols Michael R.
Yee Duke W.
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