Method and system for creating electronic circuitry

Details Method and system for creating electronic circuitry Method and system for creating electronic circuitry

1998-06-04

2001-12-04

Teska, Kevin J. (Department: 2763)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S002000, C716S030000

Reexamination Certificate

active

06327557

ABSTRACT:

TECHNICAL FIELD
This patent application relates in general to electronic circuitry and in particular to a method and system for creating electronic circuitry.
BACKGROUND
Increasing density, complexity and speed of integrated electronic circuitry has resulted in a need for higher accuracy tools that support creation of designs for such circuitry, along with a need for higher speed tools to accommodate restricted schedules for creating such designs. One type of tool is a characterization tool for characterizing various cells of the circuitry. A cell is, for example, a component that performs a logical operation within the circuitry.
A characterization tool outputs characterization information that describes a cell's operations in response to various conditions. In response to such characterization information, a human designer may predict whether the circuitry will meet performance requirements. If such characterization information is inaccurate, the designer's prediction may likewise be inaccurate. If a design is manufactured based upon an inaccurate prediction, significant wasted time and monetary expense may be incurred.
SPICE is a generic name of a tool that includes a software program for modeling, in a relatively accurate manner, operations of cells in response to specified conditions. To achieve such accuracy, SPICE consumes a relatively high level of computational resources. Accordingly, execution of SPICE may result in substantial time delays.
In view of such delays, practical limits are imposed on the extent to which a human designer may rely upon SPICE for modeling a cell's operations in response to a wide variety of conditions. Rather than using SPICE for modeling a cell's operations in response to all likely conditions, a previous technique relies upon the designer to specify a number of representative conditions. According to such a technique, SPICE is executed for modeling the cell's operations in response only to the specified conditions.
A different tool, which is less computationally-intensive than SPICE, is executed for modeling the cell's operations in response to other conditions, thereby conserving computational resources and time. Nevertheless, unless the designer already knows the expected operations of the cell in response to various conditions, it is difficult and, in some cases, impractical for the designer to accurately determine which conditions should be specified as being the most representative. Accordingly, a cell's operations as estimated by the different tool may deviate by more than two percent (2%) from the cell's operation as estimated by SPICE. For conditions distant from the specified conditions, the deviations between SPICE estimates and the different tool's estimates may reach ten percent (10%) or more.
Accordingly, a need has arisen for a method and system for creating electronic circuitry, in which cells of the circuitry are characterized with higher accuracy relative to previous techniques. Also, a need has arisen for a method and system for creating electronic circuitry, in which cells of the circuitry are characterized with higher speed relative to previous techniques.
SUMMARY
According to a first model of an operation of circuitry, a first set of estimates of the operation is generated in response to a set of conditions, including a first estimate of the operation in response to a first condition. According to a second model of the operation, a second set of estimates of the operation is generated in response to the first condition and the first set. In response to a comparison between the first estimate and the second set, a subset of the first set is selected. According to the second model, an estimate of the operation is generated in response to a second condition and the selected subset.
It is a technical advantage that cells of the circuitry are characterized with higher accuracy relative to previous techniques.
It is another technical advantage that cells of the circuitry are characterized with higher speed relative to previous techniques.


REFERENCES:
patent: 5373457 (1994-12-01), George et al.
patent: 5774382 (1998-06-01), Tyler et al.
Croix et al, “A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis”, IEEE Proceedings of the 34th Design Automation Conference, pp. 337-340, Jun. 1997.*
Menezes et al, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp. 690-695, Jun. 1995.*
John F. Croix, D.F. Wong, “A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis”, Jun. 9, 1997.

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