Boots – shoes – and leggings
Patent
1996-11-01
1999-02-09
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364490, 364491, G06F 1750
Patent
active
058703080
ABSTRACT:
A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. Techniques are described for estimating ancillary parameters of the device (such as device cost, production speed, production lead time, etc.), at early, high level stages of the design process (e.g., at the system, behavioral, and register transfer level stages). The techniques can be applied to optimize the design characteristics other than measurable physical characteristics, such as those deriving from project time and cost constraints.
REFERENCES:
patent: T940008 (1975-11-01), Oden
patent: T940020 (1975-11-01), Brechling et al.
patent: 4353117 (1982-10-01), Spellman
patent: 4587625 (1986-05-01), Marino, Jr. et al.
patent: 4635208 (1987-01-01), Coleby et al.
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4697241 (1987-09-01), Lavi
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4789944 (1988-12-01), Wada et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4813013 (1989-03-01), Dunn
patent: 4827427 (1989-05-01), Hyduke
patent: 4831543 (1989-05-01), Mastellone
patent: 4833619 (1989-05-01), Shimizu et al.
patent: 4890238 (1989-12-01), Klein et al.
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4965741 (1990-10-01), Winchell et al.
patent: 4967367 (1990-10-01), Piednoir
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5034899 (1991-07-01), Schult
patent: 5084824 (1992-01-01), Lam et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5164908 (1992-11-01), Igarashi
patent: 5164911 (1992-11-01), Juran et al.
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5572436 (1996-11-01), Dangelo et al.
Thomas et al. ("The System Architect's Workbench", 1988 DAC Draft Submission, 4 Nov. 1987, 10 pages.
Jain et al. ("Experience with the ADAM Synthesis System", 26th ACM/IEEE Design Automation Conference, 1989, pp. 56-61.
Friedman et al. ("Methods Used in an Automatic Logic Design Generator (ALERT)", IEEE Transactions on Computer, vol. C-18, No. 7, Jul. 1969, pp. 593-614).
Brewer, F.D. Et al. ("Knowledge based control in micro-architecture design," Proc. of the 24th Design Automation Conf., New York, NY:ACM/IEEE, Jun. 1987, pp. 203-209).
DeGroat et al.("The AFIT VHDL environment", IEEE, 1988 Frontiers in Education Conference, 22 Oct. 1988, pp. 324-329).
Chawla et al. ("An investigation of the performance of a distributed functional digital simulator", IEEE, Proceedings of the 32nd Midwest Symposium on Circuits and Systems, 14 Aug. 1989, vol. 1, pp. 470-473).
De Micheli et al. ("HERCULES--a system for high-level synthesis", IEEE, 25th ACM/IEEE Design Automation Conference, 12 Jun. 1988, pp. 483-488).
Fujimoto ("Parallel discrete even simulation", Communications of the ACM, Oct. 1990, pp. 30-54).
Lahti et al. ("SADE: a graphical tool for VHDL-based system analysis", IEEE Comput. Soc. Press, 1991 IEEE International Conference on Computer-Aided Design, Digest of Technical Papers, 11 Nov. 1991, pp. 262-265).
Lis et al. ("Synthesis from VHDL", IEEE Comput. Soc. Press, Proceedings of the 1988 International Conference on Computer Design: VLSI in Computers and Proceedings--ICCD 1988, 3 Oct. '88, pp. 378-381).
Lampard, M. ("System 1076--a graphical VHDL design environment", IEE, IEE Colloquium on `High Level Modeling and Design for ASICs`, 27 Oct. 1989, pp. 6/1-3).
Marwedel, P. ("A new synthesis algorithm for the MIMOLA software system", Proceedings of the 23rd Design Automation Conf. New York, NY: ACM/IEEE, Jun. 1986, pp. 271-277).
McFarland, M. C. ("Reevaluating the Design Space for Register-Transfer hardware Synthesis", IEEE, International Conference on Computer-Aided Design, Nov. 1987, pp. 262-265).
McFarland, M.C. et al., ("Assisting DAA: The Use of Global Analysis in an Expert System", IEEE, International Conference on Computer-Aided Design, Oct. 1986, pp. 482-485).
McFarland, M. C. Et al. ("Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions", Proceedings of the 23rd Design Automation Conf. New York, NY: ACM/IEEE, Jun. 1986, pp. 474-480).
McFarland, M. C. et al. ("The high-level synthesis of digital systems", Proceedings of the IEEE, vol. 78, No. 2, Feb. 1990, pp. 301-318).
Park, N. et al. ("Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications", IEEE Transactions on Computer-Aided Design, vol. 7, No. 3, Mar. 1988, pp. 356-370).
Parker, A. C. Et al., ("MAHA: A Program for Datapath Synthesis," Proceedings of the 23rd. Design Automation Conf. New York, NY: ACM/IEEE, Jun. 1986, pp. 461-466).
Paulin, P. G. et al. ("Force-directed scheduling for the behavioral synthesis of ASICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, No. 6, Jun. 1989, pp. 661-679).
Rundensteiner, E. A. Et al. ("Functional synthesis using area and delay optimization", IEEE Comput. Soc. Press, Proceedings of the 29th ACM/IEEE Design Automation Conference, 8 Jun. 1992, pp. 291-296).
Sio, M. C. et al. ("Systems aspects of windows", IEEE, Fourth IEEE Region 10 International Conference: Information Technologies for the 90's E2C2; Energy, Electronics, Computers, Communications, 22 Nov. 1989, pp. 979-982).
"Tango-Schematic Capture Software," PERX Catalog, pp. 18 & 19, No date.
"Methods Used in an Automatic Logic Design Generator (ALERT)", by Friedman et al., IEEE Transactions on Computers, vol. C18, No. 7, Jul. 1969, pp. 593-614.
"Quality of Designs from an Automatic Logic Generator (ALERT)," by Friedman et al., IEEE Design Automation Conference, 1970, pp. 71-80.
"Design Automation," by Russo, Computer, May/Jun. 1972, pp. 19-22.
"Computer Aided Design," by Lynn, Computer, May/Jun. 1972, pp. 36-45.
"Recent Developments in Design Automation," by Breuer, Computer, May/Jun. 1972, pp. 23-35.
"LINDA: A Local Interactive Design Aid for Computer-Aided General-Purpose Artwork Production," By Briggs, GEC Journal of Science & Technology, vol. 43, No. 2, 1976.
"An Engineering System for Designer, Manager and Manufacturer," by Smith et al., Telesis, vol. 4, No. 9, Dec. 1976, pp. 268-273.
"Computer Graphics In Power Plant Design," By Strong et al., IEEE Power Engineering Society, Jul. 1978.
"An Automated System to Support Design Analysis," by Willis, 12th Annual Asilomar Conference on Circuits, Systems & Computers, IEEE, Nov. 1978, pp. 646-650.
"Computer-Aided Partitioning of Behavioral Hardware Descriptions," by McFarland, 20th Design Automation Conference, IEEE, 1983, pp. 472-478.
"Definite Clause Translation Grammars," by Abramson, University of British Columbia, IEEE, 1984, pp. 233-240.
"VERIFY: A Program for Proving Correctness of Digital Hardware Designs," by Barrow, Artificial Intelligence 24, 1984, pp. 437-483.
"Switch-Level Delay Models for Digital MOS VLSI," by Ousterhout, IEEE 21st Design A
Dangelo Carlos
Nagasamy Vijay
Ponukumati Vijayanand
Kik Phallaka
LSI Logic Corporation
Teska Kevin J.
LandOfFree
Method and system for creating and validating low-level descript does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for creating and validating low-level descript, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for creating and validating low-level descript will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1955421