Boots – shoes – and leggings
Patent
1994-02-10
1996-09-10
Trans, Vincent N.
Boots, shoes, and leggings
364488, 364578, G06F 1750
Patent
active
055552013
ABSTRACT:
A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "modules" of the design and design hierarchy. The user can specify a level of detail to be displayed for any design element or group of design elements. Any CDFG (control and dataflow graph) object can be "annotated" with a visual attribute or with text to indicate information about the design elements represented by the object. For example, block size, interior color, border color, line thickness, line style, etc., can be used to convey quantitative or qualitative information about a CDFG object. Examples of information which can be used to "annotate" objects include power dissipation, propagation delay, the number of HDL statement represented, circuit area, number of logic gates, etc. The user is able to expand and/or compress CDFG blocks either "in-place" on a higher level CDFG display or to be displayed in isolation. Simulation-related data can also be used to annotate the CDFG. By viewing CDFG's (particularly annotated CDFG's) for a variety of trial designs, a problem-solving user can gain quick insight into the effects and effectiveness of various design choices.
REFERENCES:
patent: T940008 (1975-11-01), Oden
patent: T940020 (1975-11-01), Brechling
patent: 4353117 (1982-10-01), Spellmann
patent: 4587625, Marino, Jr. et al.
patent: 4635208 (1987-01-01), Coleby et al.
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4697241 (1987-09-01), Lavi
patent: 4703435 (1987-10-01), Daarringer et al.
patent: 4789944 (1988-12-01), Wada et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4818013 (1989-03-01), Dunn
patent: 4827427 (1989-05-01), Hyduke
patent: 4831543 (1989-05-01), Mastellone
patent: 4833619 (1989-05-01), Shimizu et al.
patent: 4890238 (1989-12-01), Klein et al.
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4965741 (1990-10-01), Winchell et al.
patent: 4967367 (1990-10-01), Piednoir
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5034899 (1991-07-01), Schult
patent: 5084824 (1992-01-01), Lam et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5164911 (1992-11-01), Juran et al.
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 6164908 (1992-11-01), Igarashi
"Tango-Schematic Capture Software", PERX Catalog, pp. 18 & 19.
"Methods Used in an Automatic Logic Design Generator (ALERT)", by Friedman et al., IEEE Transactions On Computers, vol. C18, No. 7, Jul. 1969, pp. 593-614.
"An Efficient Heuristic Procedure for Partitioning Graphs", by Kernighan et al., The Bell System Technical Journal, Feb. 1970, pp. 291-306.
"Quality of Designs From An Automatic Logic Generator (ALERT)", by Friedman et al., IEEE Design Automation Conference, 1970, pp. 71-80.
"Design Automation", by Russo, Computer, May/Jun. 1972, pp. 19-22.
"Computer Aided Design", by Lynn, Computer, May/Jun. 1972, pp. 36-45.
"Recent Developments in Design Automation", by Breuer, Computer, May/Jun. 1972, pp. 23-35.
"LINDA: A Local Interactive Design Aid For Computer-Aided General-Purpose Artwork Production", by Briggs, GEC Journal of Science & Technology, vol. 43, No. 2, 1976.
"An Engineering System for Designer, Manager and Manufacturer", by Smith et al., Telesis, vol. 4, No. 9, Dec. 1976, pp. 268-273.
"Computer Graphhics In Power Plant Design", by Strong et al., IEEE Power Engineering Society, Jul. 1978.
"An Automated System to Support Design Analysis", By Willis, 12th Annual Asilomar Conference on Circuits, Systems & Computers, IEEE, Nov. 1978. pp. 646-650.
"Computer-Aided Partitioning of Behavorial Hardware Descriptions", by McFarland, 20th Design Automation Conference, IEEE, 1983, 472-478.
"Definite Clause Transaction Grammars", by Abramson, University of British Columbia, IEEE, 1984, pp. 233-240.
"VERIFY: A Program for Proving Correctness of Digital Hardware Designs", by Barrow, Artificial Intelligence 24, 1984, pp. 437-483.
"Switch-Level Delay Models For Digital MOS VLSI", by Ousterhout, IEEE 21st Design Automation Conference, 1984, pp. 542-548.
"Automation Generation of Digital System Schematic Diagrams", by Arya et al., 22nd Design Automation Conference, IEEE, 1985, pp. 388-395.
"Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions", by McFarland, 23rd Design Automation Conference, IEEE, 1986, pp. 474-480.
"Partitioning Before Logic Synthesis", by Camposano et al., IBM Thomas J. Watson Research Center, IEEE, 1987, pp. 324-326.
"Partitioning and Placement Technique for CMOS Gate Arrays", by Odawara et al., IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 3, May 1987, pp. 355-363.
"Partitioning A Design in Structural Synthesis", by Camposano et al., IBM Watson Research Center, IEEE, 1987, pp. 564-566.
"The System Architect's Workbench", by Thomas et al., 1988 DAC Draft Submission, Nov. 1987.
"Formal Verification of Digital Circuits Using Hybrid Simulation", by Srinivas et al., IEEE Circuits and Devices Magazine, Jan. 1988, pp. 19-26.
"Tektronix Design Automation products", 1988 pp. 83-90.
"Formal Verification of the Sorbel Image Processing Chip", by Narendran et al., 25th ACM/IEEE Design Automation Conference, 1988, pp. 211-217.
"Chip Simulation Is All A Matter of Image", by Thacker et al., ESD: THE Electronic System Design Magazine, Nov. 1988, pp. 65-70.
"Area-Time Model for Synthesis of Non-Pipelined Designs", by Jain et al., CH2657-5 1988 IEEE, pp. 48-51.
"CAD For System Design: Is It Practical?", IEEE Design & Test of Computers, Apr. 1989, pp. 46-55.
"Architectural Partitioning for System Level Design", by Lagnese et al., 26th ACM/IEEE Design Automation Conference, 1989, pp. 62-67.
"Here's Software To Speed Vector Creation", by Beaverton, Electronics, May 1989, pp. 48-52.
"Here's An Easy Way To Test ASICS", by McLeod, Electronics, May 1989, pp. 116-117.
"Experience woth the ADAM Synthesis System", by Jain et al., 26th ACM/IEEE Design Automation Conference, 1989, pp. 56-61.
"Chippe: A System for Constraint Driven Behavioral Synthesis", by Brewer et al., IEEE Transactions on Computer-Aided Design, vol. 9, No. 7, Jul. 1990, pp. 681-695.
"BAD: Behavioral Area-Delay Predictor", by Kucukcakar et al., Ceng Technical Report 90--31, Nov. 1990.
"HYPER-LP: A System for Power Minimization Using Architectural Transformations", by Chandrakasan et al., IEEE, 1992, pp. 300-303.
"The CAR System: Multimedia In Support Of Collaboartive Design", by Handley, IEE Colloquium on `Multimedia and Professional Applications`, Digest No. 026, P. 8/1-5, 1993.
"Coordination And Control For Collaborative Workstation Design", by Pendergast et al., Cambridge Univ. Pres., vii+456 pp. 1991.
"PICTIVE--An Exploration In Participatory Design", by Muller, Conference Proceedings, CHI 91, pp. 225-231, 1991.
"Prototyping Approach Of Multi-Actors Computer Aided Design For Buildings In The Frame Of The CIBAO Project", by Dubois, EuropIA, pp. 338-50, 1990.
Dangelo Carlos
Mintz Doron
Watkins Daniel
LSI Logic Corporation
Trans Vincent N.
LandOfFree
Method and system for creating and validating low level descript does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for creating and validating low level descript, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for creating and validating low level descript will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1326021