Static information storage and retrieval – Powering
Reexamination Certificate
2001-03-14
2002-04-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Powering
C365S198000, C326S083000, C327S170000
Reexamination Certificate
active
06366520
ABSTRACT:
TECHNICAL FIELD
This invention relates integrated circuits, and, more particularly, to a method and system for controlling the slew rate of a signal applied to a transmission line using open drain technology to minimize inductive voltage transients internal to packaged devices and minimize other voltage asperties coupled to the transmission line.
BACKGROUND OF THE INVENTION
As the operating speed of electronic systems, such as computer systems and memory devices, continue to increase, the speed at which digital signals must be coupled continues to increase. As a practical matter, the speed at which a digital signal may be coupled through a signal line is reduced if the signal is reflected from various nodes in the signal line, such as connections to the signal line by various electronic circuits. Reflection of digital signals may be avoided by coupling the digital signals through a transmission line having an impedance matched to the impedance of circuitry coupled to the line. Electronic circuits can be designed to be impedance matched to a transmission line in this manner if the number of electronic circuits coupled to the line and the impedance of such circuits remains fixed. However, it is common to vary the number of electronic circuits coupled to a signal lines. For example, in computer systems, the number of memory modules coupled to a memory controller through a data bus, address bus, and control bus may vary. If these buses are impedance matched to the memory modules when the computer system is initially placed in service, the buses may not be impedance matched when additional memory modules are coupled to the buses.
One conventional approach to allowing a varying number of electronic devices to be coupled to a transmission line while maintaining impedance matching between the devices and the line is through open drain technology. The principle of open drain technology can be explained with reference to FIG.
1
. As shown in FIG.
1
, a memory controller
10
generating a binary signal is coupled to one end of a transmission line
14
. An opposite end of the transmission line
14
is coupled to a voltage source
16
through a terminating resistor
18
. For purposes of illustration, the voltage of the voltage source
16
is assumed to be 1.5 volts, although it may be any voltage in practice. The resistance of the terminating resistor
18
is substantially the same as the characteristic impedance Z
0
of the transmission line
14
. For purposes of illustration, the characteristic impedance Z
0
of the transmission line
14
and the resistance of the resistor
18
is assumed to be 20 ohms. The signal generated by the memory controller
10
is a switched current signal that switches between two values of current. For example, one binary value may be represented by a current of 0 ma., and the other binary value may be represented by a current of 25 ma. Under these circumstances, a voltage V
0
at a node
20
to which the transmission line
14
is coupled will switch between 1.5 volts when the current is 0, and 1.0 volt when the current is 25 ma. The voltage V
0
at the node
20
thus switches between two levels to represent respective binary values. Also coupled to the transmission line
14
at a plurality of respective nodes
22
a,b . . . n
are memory devices
24
a,b . . . n
, which also output a switched current signal.
Although the voltage at the nodes
20
and
22
a,b . . . n
switch between two values, the effect of doing so by varying the current between two values is significantly different from simply using a switched voltage source to drive the voltage applied to the nodes
20
and
22
a,b . . . n
between two values. If, for example, the memory device
24
b
outputs a switched voltage signal on the transmission line
14
, the signal will propagate through the transmission line
14
away from the memory device
24
b
in both directions. When the signal reaches the memory controller
10
, it will be reflected from node
20
because of the impedance mismatch between the 25 ohm characteristic impedance of the transmission line
14
and the high impedance at the input to the inactive memory controller
10
. By the time the reflected signal reaches the memory device
24
a
, the memory device
24
a
may be outputting a signal. If the memory device
24
a
was outputting a switched voltage signal, the voltage at the node
22
a
would remain constant despite the reflected signal reaching the node
22
a
because the memory device
24
a
would draw or provide sufficient current to maintain the voltage substantially constant. The magnitude of an impedance from an A.C. or transient point of view is proportional to the ratio of the change in voltage to the change in current. Consequently, the input impedance of the memory device
24
a
resulting from a small change in voltage and a large change in current is relatively small. The low impedance of the memory device
24
a
would cause further reflection of signal from the node
22
a
. Furthermore, the impedance at each node
22
a,b . . . n
would change greatly depending upon whether a memory device
24
a,b . . . n
was coupled to the node
22
a,b . . . n.
If a signal was reflected from the memory controller
10
and the memory device
24
a
was outputting a current switched signal, the effect would be substantially different. In such case, the voltage at the node
22
a
would change responsive to the reflected signal reaching the node
22
a
because the memory device
24
a
maintains the current substantially constant. Consequently, the input impedance of the memory device
24
a
resulting from a relatively large change in voltage and a very small change in current is relatively large. In fact, the impedance of the memory device
24
a
may be so large that the memory device
24
a
has no effect on the signal reflected from the memory controller
10
. Under these circumstances, the memory device
24
a
does not even electrically appear to be coupled to the transmission line
14
. The memory devices
24
a,b . . . n
can therefore be added or removed to the transmission line
14
without altering the performance of the transmission line
14
.
In practice, the memory controller
10
and the memory devices
24
are able to drive the transmission line
14
with a switched current signal through a drain of a MOSFET transistor (not shown) that is “open” or unconnected to any other circuitry. The advantages of using this open drain technology are not entirely without some countervailing disadvantages. One disadvantage is the switching of current supplied or drawn by an open drain device generally results in a corresponding change in the power supply current drawn by the device. This change in current drawn by the device through inductive power supply lines (not shown) can produce voltage transients on the power supply lines that result in power supply noise. Such power supply noise can adversely affect the operation of other circuitry in the open drain device as well as other devices that are coupled to the same power source.
The magnitude of a voltage transient is proportional to the inductance of a power supply line through which the current is drawn and the first derivative of the current through the line as a function of time. Thus, reducing the rate of current change, i.e., the first derivative of the current, reduces the magnitude of the voltage transients generated in a power supply line. One approach to reducing the rate of current change in an open drain device will be explained with reference to
FIGS. 2 and 3
. As shown in
FIG. 2
, an open drain device outputs a switched current signal I that changes from I
0
to I
1
and then subsequently back to I
0
. The switched current signal I results in a voltage E that changes correspondingly from E
0
to E
1
and then subsequently back to E
0
. As also shown in
FIG. 2
, the first derivative I′ of the current signal I is a positive pulse coincident with the leading edge of the switched current signal and a negative pulse coincident with the falling edge of the switched curre
Dorsey & Whitney LLP
Le Vu A.
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