Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Reexamination Certificate
1999-11-09
2003-07-29
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
C709S227000, C709S233000, C370S230000, C370S259000
Reexamination Certificate
active
06601105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates: in general to high frequency digital systems and, in particular, to controlling the flow of information between a producer and multiple buffers in a high frequency digital system. Still more particularly, the present invention relates to a method and system for controlling the flow of information from a memoriless producer to multiple buffers in a high frequency digital system.
2. Description of the Related Art
As processor micro-architectures are optimized toward implementations that support higher clock frequencies, the complexity of the work that can be performed within each clock cycle decreases. This phenomenon has a tendency to introduce increased cycle-time latency into mechanisms which control the flow of information between components in the micro-architecture, effectively delaying critical feedback within such mechanisms and eroding the aggregate bandwidth of the information flow.
This bandwidth erosion occurs when the buffering capacity of downstream components approaches full occupancy, such that the fill time of the remaining available capacity approaches the latency of feedback in the information flow control mechanism. In such cases, the information flow control mechanism often must pessimistically assume worst case information flow to avoid exceeding the buffering capacity of the downstream components. Thus, for example, the information flow control mechanism may assume that information is being sent (and stall information flow appropriately based on downstream capacity considerations) whether or not information is actually sent in order to avoid overflowing the downstream buffers.
In many cases, such bandwidth erosion can be averted by increasing the buffering capacity of downstream components to minimize the likelihood that high utilizations will dictate precautionary stalls. However, an increase in buffering capacity also raises component cost without providing additional benefit beyond a reduction in bandwidth erosion. In other cases, more sophisticated flow protocols can be introduced, which tolerate information loss due to aggressive capacity speculation by incorporating retry mechanisms. However, such mechanisms can greatly increase complexity, thus inhibiting design verification and testability. Moreover, retry protocols also increase the utilization of the upstream component, possibly requiring an increase in its size and cost.
The present invention offers an attractive alternative for addressing the obstacles to efficient information flow that arise in high frequency digital systems that control, monitor, or perform transformations on streaming information.
SUMMARY OF THE INVENTION
In accordance with the present invention, an information handling system, such as a processor, includes a producer that outputs packets of information, a plurality of buffers that can each receive packets from the producer and output the packets, and a control unit. The control unit receives at least one producer output indication indicating whether the producer output a packet to one of the plurality of buffers and a plurality of buffer output indications that each indicate whether a respective one of the plurality of buffers has output a packet. Based upon capacities of the plurality of buffers, the producer output indications, the buffer output indications and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. If so, the control unit provides a grant message to the producer indicating that the producer is permitted to output a packet.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5291481 (1994-03-01), Doshi et al.
patent: 5392280 (1995-02-01), Zheng
patent: 5646943 (1997-07-01), Elwalid
patent: 5650994 (1997-07-01), Daley
patent: 5898670 (1999-04-01), Hoebeke et al.
patent: 5938749 (1999-08-01), Rusu et al.
patent: 5996013 (1999-11-01), Delp et al.
patent: 6052738 (2000-04-01), Muller et al.
patent: 6259698 (2001-07-01), Shin et al.
patent: 6438104 (2002-08-01), Fodor et al.
Sakurai,et al., “Large-Scale ATM Multistage Switching Network With Shared Buffer Memory Switches,” IEEE Communications, vol. 29, pp. 90-96, Jan. 1991.
Fong, et al., “Analytical Modeling of Multistage ATM Switches With Backpressure Control Schemes”, Broadband Switching Systems Proceedings, 1997, IEEE BSS '97, 2nd IEEE International Workshop.
Bell, Jr. Robert Henry
Cargnoni Robert Alan
Clark Leo James
Starke William John
An Meng-Al T.
International Business Machines - Corporation
Lin Wen-Tai
Volel Emile Bracewell & Patterson, L.L.P.
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