Method and system for controlling a tuning voltage of a...

Details Method and system for controlling a tuning voltage of a... Method and system for controlling a tuning voltage of a...

2000-11-01

2001-12-11

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S025000, C327S156000

Reexamination Certificate

active

06329883

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a phase-locked loop (“PLL”) circuit, and, in particular, to a linear control loop for controlling a tuning voltage of a PLL circuit. Still more particularly, the present invention relates to a method and system for controlling a tuning voltage of a PLL circuit to an optimal value.
2. Description of the Related Art
A phase-locked loop (“PLL”) circuit is generally a circuit that has an oscillator, which outputs a phase that automatically adjusts in synchronization with an input oscillator signal. The PLL circuit receives an input reference frequency from a signal and outputs a signal having a frequency that is a multiple of the input reference frequency. The PLL circuit is utilized to lock the output frequency to be in phase with the input frequency. Locking the output and input frequencies to be in phase is very critical in developing accurate and precise clocks that are used by digital signal processors (“DSPs”) and for audio sampling frequencies and rates.
Various non-ideal factors (“non-idealities”), such as temperature, supply voltage, non-typical process parameters, etc., may affect the operation of the PLL circuit. A tuning voltage circuit is coupled to the PLL circuit to adjust and/or control the tuning voltage for the PLL circuit in eliminating or minimizing the effects of the non-idealities on the operation of the PLL circuit. Various tuning voltage circuits for PLL circuits exist.
With reference now to
FIG. 1
, an exemplary tuning voltage (“TV”) circuit
100
, that is a digital control loop, for a PLL circuit
101
is shown. TV circuit
100
and PLL circuit
101
are driven by a power source(s) V
s
and are also coupled to ground. TV circuit
100
has a first voltage comparator
128
, a second voltage compartor
132
, a digital control unit
136
, and a discrete current source
140
. First and second voltage comparators
128
and
132
are coupled to inputs of digital control unit
136
, and discrete current source
140
is coupled to an output of digital control unit
136
. PLL circuit
101
includes a phase detector
106
, a loop filter
110
, a voltage-to-current (“V-TO-I”) converter
112
, a current adder
116
, and a current controlled oscillator (“ICO”)
120
coupled together in series. Tuning voltage (“TV”)
126
is the voltage level at the output of loop filter
110
and the input of V-to
4
converter
112
. TV
126
is fed into a positive input terminal
128
A of first voltage comparator
128
, and a maximum reference voltage (“VMAX”)
124
is fed into a negative input terminal
128
B of first voltage comparator
128
. Furthermore, TV
126
is fed into a negative input terminal
132
A of second voltage comparator
132
, and a minimum reference voltage (“VMIN”)
122
is fed into a positive input terminal
132
B. The values for VMIN
122
and VMAX
124
are determined and set by design methods and factors that are known in the art. An optimal voltage (“VOPTIMUM”)
208
(see
FIG. 2
) is also defined for TV
126
, which may be defined as the half-way value between VMIN
122
and VMAX
124
. An IBIAS(N) current
142
outputted from discrete current source
140
is fed into current adder
116
.
Reference phase &phgr;
i
102
of an input frequency signal is fed into phase detector
106
. Phase detector
106
compares reference phase &phgr;
i
102
with a fed-back output phase signal (“&phgr;
0
”)
104
from ICO
120
. Phase detector
106
generates a phase error (“&phgr;
e
”)
108
, which is the difference in phase between what the phase of the signal currently is (e.g., phase signal “&phgr;
0
104
) and what the phase should be based on reference phase &phgr;
i
102
. Phase error (“&phgr;
e
”)
108
is sent to loop filter
110
. Loop filter
110
filters voltages by passing some voltages at certain frequencies while attenuating other voltages at other frequencies. Loop filter
110
provides TV
126
. TV
126
is inputted into V-to-I converter
112
, and V-to-I converter
112
converts TV
126
to a tuning current (“ITUNE”)
114
. ITUNE
114
is passed to current adder
116
, which adds a bias current (“IBIAS(I)”)
142
, if any, based on any difference between TV
126
and a normal operating or optimum voltage, from TV circuit
100
. Current adder
116
outputs a current (“IICO”)
118
for controlling current-controlled oscillator (“ICO”)
120
. IICO
118
is inputted into ICO
120
. ICO
120
provides an output phase &phgr;
0
104
that is supposedly synchronized in phase with reference phase &phgr;
i
102
and which is also fed back to phase detector
106
to check for any further phase error.
Referring now to
FIG. 2
, graph
200
for the current-voltage characteristics of IICO
118
and TV
126
for TV circuit
100
and PLL circuit
101
of
FIG. 1
is shown. TV
126
is defined with the boundary values of VMIN
122
and VMAX
124
, which are the voltage values set for TV
126
and that TV
126
is to be kept within during the operation of PLL circuit
101
. In
FIG. 2
, graph
200
shows that, under normal operation, PLL circuit
101
follows the characteristic of IBIAS(NORMAL)+ITUNE curve
215
. Since TV circuit
100
is a digital control loop, IBIAS(I)
142
is interjected in discrete intervals (e.g., discrete IBIAS current increments) by TV circuit
100
from a zero discrete value to “N” discrete values. An “I” variable is defined as the variable value
138
in
FIG. 1
for IBIAS(I)
142
that may be varied from integer values “0 to N” for representing the number of IBIAS increments that needs to be injected to ITUNE
114
. For each IBIAS increment of IICO
118
, ITUNE curve
212
with no IBIAS increment, in effect, is displaced by and re-plotted at a next incremental IBIAS current value(s) from ITUNE curve
212
. Graph
200
illustrates the discrete increments by showing current-voltage curves
212
to
220
(e.g., ITUNE
212
; “IBIAS
1
+ITUTNE”
214
; “IBIAS
2
+ITUNE”
216
. . . “IBIAS(NORMAL)+ITUNE
215
” . . . “IBIAS(N−1)+ITUNE”
218
; “IBIAS(N)+ITUNE”
220
) plotted parallel to each other, in which each curve is separated from the other by an incremental IBIAS current value.
The optimal point under normal operation of PLL circuit
101
is at point A on curve IBIAS(NORMAL)+ITUNE curve
215
. Point A represents TV
126
equal to VOPTIMUM
208
. However, PLL circuit
101
may not typically operate under normal conditions, and non-idealities may cause PLL circuit
101
to operate along IBIAS
1
+ITUNE curve
214
at point B. TV
126
is then set at a locked TV value
209
, which corresponds to a locked IICO current
222
, under which PLL circuit
101
operates. When further non-idealities are introduced into PLL circuit
101
, TV
126
may increase or decrease in value. TV
126
may increase or decrease in value such that, before reaching VMAX
124
or VMIN
122
, operation of PLL circuit
101
is immediately and respectively forced to move up or down to another curve (e.g., move up to IBIAS(I+1) +ITUNE curve or move down to IBIAS(I−1)+ITUNE curve).
For example,
FIG. 2
illustrates that if TV
126
increases in value, then the operating point of PLL circuit
101
shifts from point B towards point C in which TV
126
attempts to become a “VC” value
230
that is above VMAX
124
. However, when TV
126
reaches VMAX
124
, IBIAS(I)
142
is immediately increased from IBIAS
1
to IBIAS
2
in order for PLL circuit
101
to shift from attempting to operate at point C on “IBIAS
1
+ITUNE”
214
to operating at point D on “IBIAS
2
+ITUNE”
216
. TV
126
becomes a “VD” value
232
that is again within the range between VMIN
122
and VMAX
124
and that provides the same value of IICO
118
at point C. Conversely, if TV
126
decreases in value, then the operating point of PLL circuit
101
may attempt to shift below (e.g., to the left) of VMIN
122
. IBIAS(I)
142
is then immediately decreased in order for PLL circuit
101
to shift from attempting to operate on the current curve in which the

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