Method and system for configuring an array of logic devices

Details Method and system for configuring an array of logic devices Method and system for configuring an array of logic devices

1996-10-30

1999-08-31

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

059462191

ABSTRACT:
A system and method for partial reconfiguration of a gate array includes generating a netlist by placement and routing of a logic circuit. The netlist is accessed to modify logic cells configurations created by the place and route operation. Based on the modifications, a partial configuration bitstream containing only bitstrings which implement the modified logic cells is created. The partial configuration bitstream is downloaded to the gate array, thereby effectuating a partial reconfiguration of the gate array. In an alternate embodiment, a system in accordance with the present invention includes software utilities which allow an application program executing in a system containing a programmable gate array to reconfigure the array on-the-fly. The utilities include routines for modifying the design in response to external conditions detected during run-time. This approach obviates the need for providing a set of predetermined alternate designs, allowing the application to make that determination on its own.

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