Pulse or digital communications – Synchronizers – Self-synchronizing signal
Reexamination Certificate
2006-01-17
2006-01-17
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Self-synchronizing signal
C375S361000, C375S364000, C375S220000, C341S070000, C327S165000, C327S227000, C324S10300R
Reexamination Certificate
active
06987824
ABSTRACT:
A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided. The asynchronous recovered non-return to zero signal is supplied to a data flip-flop along with the recovered clock out signal and a constant and the result is a synchronous recovered non-return to zero signal.
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Chin Stephen
Pathak Sudhanshu C.
Salys Casimer K.
Tkacs Stephen R.
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