Television – Bandwidth reduction system – Data rate reduction
Patent
1994-03-30
1995-09-12
Britton, Howard W.
Television
Bandwidth reduction system
Data rate reduction
348717, 348718, H04N 726
Patent
active
054501300
ABSTRACT:
A method and system for compressing color video or other image data for transmission over a low cost, low bandwidth bus (or other transmission link). Preferred embodiments implement lossless compression and include a frame buffer for storing data compressed in accordance with the invention, and circuitry for decompressing and transforming compressed data read from the frame buffer. The image data are typically organized as a sequence of frames, each comprising a sequence of pixels. Data compressed in accordance with the invention are stored in cells in memory, with each cell storing the same number of pixels. The inventive method is denoted as "cell based image compression" ("CBC"). Advantages of CBC include increasing available data transmission bandwidth and lowering required system power as a result of minimizing transfer of redundant color information to and from memory as well as fast random single pixel reads and writes. Some embodiments interface with a fast, narrow, single ported frame buffer, such as a RAMBUS or SDRAM memory, and compress image data not to minimize memory requirements, but to minimize bus bandwidth requirements for transferring data to and from memory. With this type of memory, all frame buffer accesses, such as host access, display refresh, and BLIT (Block Image Transfer) operations, compete on the same bus for frame buffer memory bandwidth. CBC allows frame buffers of acceptable BLIT performance whose available bandwidth is no more than slightly larger than the worst case bandwidth required to support display refresh (the worst case being no image compression). The amount of additional bandwidth available for BLIT operations and host access is variable, and depends on the compression rate of the data being transferred.
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Three-page document describing an XRAM frame buffer controller, believed to have been developed by Chips and Technologies, distributed at the Microsoft Windows .TM. Hardware Engineering Conference, held in Feb. 1994.
One-page specification sheet by Chips and Technologies, "64300/301 Wingine DGX DRAM Graphics Accelerator" (received Feb. 23-25, 1994).
Britton Howard W.
Radius Inc.
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