Method and system for calibrating a data converter

Details Method and system for calibrating a data converter Method and system for calibrating a data converter

2001-01-08

2002-09-24

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000

Reexamination Certificate

active

06456211

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic systems and more specifically to a method and system for calibrating data converters.
BACKGROUND OF THE INVENTION
The demand for high speed, high resolution analog-to-digital converters (ADCs) has led to the increasing importance of the effective calibration of pipelined ADCs. Pipelined architecture is widely used for high speed, high resolution ADCs because of its reasonable cost and low power dissipation. Circuit imperfections, however, limit the resolution of pipelined ADCs. Calibration is one of the most effective approaches for improving the resolution of high speed pipelined ADCs. Known methods and systems for calibrating pipelined ADCs, however, have not been able to achieve today's demand for high resolution.
Analog-to-digital conversion in pipelined ADCs is a multi-stage process. In the first stage, an analog input is sampled and held. The input is then converted into a digital code by a low resolution ADC (subADC) as a first approximation of the analog input. The digital code forms part of the output of the ADC, and is also converted back to an analog code by a low resolution digital-to-analog converter (subDAC). The analog code is subtracted from the analog input to yield a residue voltage. The residue voltage is amplified and sent to the second stage where this process is repeated, and so on. The digital code from the multiple stages is corrected for subADC errors and then output from the ADC.
ADC resolution is limited by two types of errors. The first type of error occurs when the residue exceeds the input range of a subsequent subADC. These errors are relatively easy to correct by using digital error correction, which reduces the gain to guarantee that the residue signal is within the range of the next subADC. The second type of error results from changes in the residue as it is propagated through an imperfect circuit from one stage to the next, and is typically corrected by calibration. These errors pose a major challenge for calibration, as it is difficult to estimate the error caused by residue changes.
Known calibration methods use the output of digital error correction to estimate the error of the ADC output. From the estimate, calibrated values are computed to correct the second type of error. One problem with these methods is that the digital error correction output does not contain information about the actual state of every stage of the pipelined process, resulting in poor error estimation and consequently poor error correction. For example, suppose there are three stages, and each stage has two-bit digital code segments, D
1
=01, D
2
=10, D
3
=01, where the digital code may be written as (01,10,01). A digital error correction output may be constructed by adding the code segments with adjacent code segments overlapping by one bit:
 
01
D1
 
 
⁢
10
D2
+
)
 
⁢
01
D3
 
1001
binary
⁢
 
⁢
output
The digital error correction output is 1001. Note that code (10,00,01) also produces a digital error correction output of 1001. From the digital error correction output 1001, it is impossible to know the state of every ADC stage, for example, the first stage could be 01 or 10. Another problem with these methods is that the they cannot provide accurate error correction for the full range of the input voltages. These methods estimate error by performing a best fit procedure on one section of the input voltage at a time. After calibration, the individual sections may have minimized error, but the whole range might not. This is especially problematic in applications that require a large dynamic range.
While these approaches have provided improvements over prior approaches, the challenges in the field of electronic systems have continued to increase with demands for more and better techniques having greater accuracy. Therefore, a need has arisen for a new method and system for calibrating data converters.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and system for calibrating analog-to-digital converters are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods.
According to one embodiment of the present invention, a system for calibrating data converters is disclosed that includes a data converter that receives an input signal and generates one or more pre-digital error correction codes from the input signal. A calibrator receives pre-digital error correction codes, formulates expressions of one or more transition voltages using the pre-digital error correction codes, and compares the transition voltage expressions to one or more measured transition voltage values to generate one or more calibrated values. More specifically, the data converter may be a pipelined analog-to-digital converter.
According to one embodiment of the present invention, a method for calibrating data converters is disclosed. First, an input signal is input into a data converter. Second, pre-digital error correction codes for the input signal are provided by the data converter. Third, transition voltages are measured to yield measured transition voltage values. Fourth, transition voltage expressions are formulated using the pre-digital error correction codes. Fifth, calibrated values are calculated by comparing the transition voltage expressions to the measured transition voltage values. Finally, the data converter is calibrated using the calibrated values.
A technical advantage of the present invention is that it uses pre-digital error correction codes, which directly reflect the behavior of every ADC stage, and therefore contain more error information. Consequently, the use of pre-digital error correction codes increase the accuracy of the calibration, thus improving the performance of ADCs. Another technical advantage of the present invention is that it determines the best fit for the full range of input voltages, resulting in a better approximation over the whole range, which is especially important for applications that require a large dynamic range. Another technical advantage of the present invention is that it not only corrects the errors resulting from when the residue exceeds the input range of a subsequent subADC but also corrects errors from changes in the residue as it is propagated through an imperfect circuit from one stage to the next. This eliminates the need for a separate digital error correction module. Another technical advantage of the present invention is that it poses no additional requirements on pipelined ADC design. The only requirement is that pre-digital error correction codes are accessible during the calibration mode. Other technical advantages are readily apparent to one of skill in the art.


REFERENCES:
patent: 5861828 (1999-01-01), Opris
patent: 5929796 (1999-07-01), Opis et al.
patent: 6097326 (2000-08-01), Opris et al.

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