Patent
1997-09-18
1999-05-04
Ray, Gopal C.
G06F 1314
Patent
active
059012943
ABSTRACT:
A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a number of sub-buses. A maximum number of sub-buses is specified for each processor and the processors are prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maximum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.
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Kahle James Allan
Tran Cang Ngoc
Dillon Andrew J.
England Anthony V.S.
International Business Machines - Corporation
Ray Gopal C.
LandOfFree
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