Method and system for buffering a data packet for...

Multiplex communications – Pathfinding or routing – Store and forward

Reexamination Certificate

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Details

C370S352000, C370S395720, C710S027000, C711S219000

Reexamination Certificate

active

07099345

ABSTRACT:
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

REFERENCES:
patent: 6330631 (2001-12-01), Crosland

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