Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-08-02
2004-01-13
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000, C438S016000
Reexamination Certificate
active
06677169
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit device analysis, and more particularly to backside device analysis on ball grid array devices using a planar backside chip thinning system.
BACKGROUND OF THE INVENTION
With advancements in integrated circuit technology, electronic devices have become much more powerful and have shrunken in size. Devices that once occupied an entire desk top now fit into a jacket pocket. The drive toward smaller and portable electronic products has pushed the development of chip scale packages (CSPs). CSPs incorporate semiconductor devices into a compact configuration by accommodating leads connected to a circuit forming surface of a semiconductor chip within a size of the chip. For instance, CSPs are typically in the range of 1.2 times the size of the semiconductor die. Comparing the size of an 8 Mb flash memory device, such as a TSOP48 (Thin Small Outline Package), which is approximately 18.4 mm×12 mm, the size of a CSP, such as a fine pitch ball grid array (FBGA), is approximately 6 mm×9 mm.
A typical CSP is a ball grid array, which is a surface mount chip package that uses a grid of solder balls to couple the integrated circuit device to a planar, such as a circuit board. One type of ball grid array (BGA) is the fine pitch BGA (FBGA), which can incorporate a polyimide (PI) tape package substrate (FBGA-PI) or a bismaleimide triazine (BT) package substrate (FBGA-BT).
FIGS. 1 and 2
illustrate partial cross-sectional diagrams of typical FBGA devices.
FIG. 1
illustrates a single die package
10
, such as an AM29LV160DT manufactured by Advanced Micro Devices, Inc. of Sunnyvale, Calif., while
FIG. 2
illustrates a stacking two dice package
50
, known as a multi-chip package (MCP). Both packages are commonly used for memory integrated circuit devices, and the MCP is widely used for high density and mixed type memory integrated devices.
As is shown in
FIG. 1
, an FBGA package
10
includes an integrated circuit die
12
coupled to a package substrate
14
. Electrical connections for the die
12
are provided by gold bond wires
16
, which connect a plurality of bond pads
18
on the die
12
to an interconnect pattern
20
on the package substrate
14
. The interconnect pattern
20
provides an electrical path (not shown) from the bond pads
18
on the die
12
to a plurality of solder ball connectors
22
, which attach the package
10
to a planar (not shown). The die
12
and bond wires
16
are encapsulated by a molding compound
24
. A solder mask layer
26
defines the location of each solder ball
22
.
The MCP
50
, shown in
FIG. 2
, is substantially similar in structure to the single die package
10
, except that a first die
51
is stacked on a second die
52
, which in turn is coupled to the package substrate
14
′. A plurality of bond wires
16
′ couple a plurality of bond pads
18
′,
18
″ on the first die
51
and the second die
52
to the interconnect pattern
20
′, which provides an electrical path (not shown) to a plurality of solder ball connectors
22
′.
As stated above, FBGA packages such as those illustrated in
FIGS. 1 and 2
are gaining widespread use in portable electronic devices. As with all integrated circuits, testing and fault isolation analysis is essential to improving the design and performance of the semiconductor device. Conventional analysis techniques involve accessing the integrated circuit from the front, or top, side. Nevertheless, frontside analysis has become more difficult as integrated circuits have become more complex. For instance, integrated circuits are distributed and interconnected over multiple layers, and oftentimes, the active regions of the integrated circuit are buried beneath metal buses, which obscure or prevent analysis from the frontside. Access to those active regions would require destroying the upper metal layers, thereby destroying the integrated circuit. Moreover, frontside analysis is not feasible for certain CSPs, such as flip chips (e.g., micro BGAs) and MCPs incorporating stacked dice.
In response, techniques have been developed to analyze an integrated circuit from the backside, i.e. the bottom, of the semiconductor die. The sample is prepared by using a planar backside chip thinning system, such as the Chip Un-Zip ™ system manufactured by Hypervision, Inc. of Fremont, Calif., to remove any backside mold compound and to expose the backside of the semiconductor die. The backside surface of the die can be polished to facilitate backside imaging if such analysis is required. In this manner, access to the active regions in the integrated circuit is possible because the upper layers, including the metal buses, are no longer obscuring the active regions. Circuit fault isolation analysis, such as emission microscope analysis, can be performed without destroying the integrated circuit.
While backside analysis provides a reasonable alternative for most integrated circuit packages, it is not feasible for BGA packages.
FIG. 1A
illustrates the FBGA package of
FIG. 1
after conventional preparation for backside analysis. As noted above, the BGA package is connected electrically to the planar through the solder ball connectors located on the backside of the package. The backside of the die cannot be exposed for backside analysis without removing the solder ball connectors, without which, the BGA package would be electrically isolated. Thus, conventional sample preparation for backside analysis would impair electrical connectivity at the package level, i.e. electrical connection between the package and the planar. Such electrical connectivity is required for circuit fault isolation analysis, such as emission microscope analysis.
Accordingly, a need exists for a system and method for preparing a BGA device for backside analysis. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for preparing a device for diagnostic analysis is disclosed. The device to be prepared includes a semiconductor die coupled to a first surface of a package substrate, which includes an interconnect pattern for electrically coupling the die to the package substrate. The package substrate includes a plurality of solder ball connectors that are electrically connected to the interconnect pattern and are disposed on a second surface of the package substrate. The method and system for preparing the device for backside analysis comprises removing the plurality of solder ball connectors, selectively removing a first portion of the second surface of the package substrate to expose the interconnect pattern, and then selectively removing a second portion of the package substrate to expose a backside of the semiconductor die. The method further includes preparing the backside of the semiconductor die for diagnostic testing. Electrical contact with the semiconductor die is established via the exposed interconnect pattern.
Through the aspects of the present invention, backside analysis of a device which utilizes solder ball connectors, can be performed while maintaining electrical connectivity with the device. Instead of relying on the solder ball connectors, the present invention establishes electrical connectivity with the device through the interconnect pattern on the package substrate. Accordingly, the integrated circuits can be powered to perform fault isolation analysis.
REFERENCES:
patent: 5216278 (1993-06-01), Lin et al.
patent: 5821549 (1998-10-01), Talbot et al.
patent: 6245586 (2001-06-01), Colvin
patent: 6395580 (2002-05-01), Tseng
Vockrodt Jeff
Winstead Sechrest & Minick P.C.
Zarabian Amir
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