Patent
1997-01-13
1998-09-22
Heckler, Thomas M.
395557, G06F 112
Patent
active
058128352
DESCRIPTION:
BRIEF SUMMARY
This application is the national phase of international application PCT/FI95/00400, filed Jul. 10, 1995 which designated the U.S.
FIELD OF THE INVENTION
The present invention relates to a method and system for automatic compensation of line delay in a clock distribution system in which a clock generator distributes a master clock signal on clock path to a group of decentralized clock signal buffers.
BACKGROUND OF THE INVENTION
In a digital switching exchange, for example, there are a number of decentralized computer units which communicate with one another on a synchronous data transmission bus. On a synchronous bus, computer units connected to it must be synchronized with regard to one another by timing signals. As far as the operation of the data transmission bus is concerned, the aim is to distribute timing signals so that the clock signals arrive at each computer unit with substantially the same phase, or so that the clock signals have a desired phase difference.
In the distribution system of timing, i.e. clock signals, a centralized clock signal generator produces a so-called master clock signal which is distributed via one or more cabling routes to clock signal buffers which handle the distribution of clock signals to one or more decentralized computer units.
Clock signal buffers on the same clock distribution path are located at different line lengths from the clock signal generator that distributes the clock signal. In such a clock distributing system, the phase of the output clock pulse must be adjusted in each buffer so that it compensates the delay between the buffer and the clock signal generator which distributes a master clock signal to the buffer, which delay is caused by a specific cable length between them. Following the delay compensation, the clock signals received by different computers are with the same phase, or a desired time difference has been set between them.
The line delay does not have to be compensated in the clock signal distribution, if lines of fixed length are used between the clock signal buffers and the clock signal generator.
If lines of fixed length are used, buffers cannot be connected in parallel to the same clock path, but clock distribution has to carried out to each buffer on their respective cables whereupon the cables form a star-like figure.
A manual method represents one way for compensating the clock phase. In such a case, a phase preset is manually set for each clock signal buffer, the value of which depends on the length of the line section between the generator transmitting the master clock signal, and the buffer. The buffer is informed of the required buffer-specific phase preset value by, for example, back end terminals or bridge connections. A manual setting of a phase preset value like this is trying, and a high possibility exists for erroneous settings that are difficult to notice, especially if the number of required phase preset values is large for reasons of accuracy.
Another known method for carrying out compensation is to carry it out at the master clock end of the clock path. Such a system is described in the U.S. Pat. No. 5,298,866. In said patent, parallel to each clock distribution path leading from the clock distribution circuit to the buffer, a separate return path is connected to the clock distribution path just prior to the buffer. The clock distribution circuit includes a loop comprising a delay element, which loop is also fed with a clock signal, and thus the delayed clock signal acts as a reference signal. The logic compares the phase of return signals from the various clock distribution paths to the phase of the reference signal, and dynamically adjusts the phase of each outward clock signal so that it matches the phase of the reference signal. This method is restricted to be utilized in a star-like clock distribution system in which clock paths are of different lengths.
The Canadian Patent CA-1 301 261, Grover, describes carrying out compensation in a case in which the application modules to be synchronized are on the same cloc
REFERENCES:
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5361277 (1994-11-01), Grover
Heckler Thomas M.
Nokia Telecommunications Oy
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