Method and system for automated die yield prediction in semicond

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395500, 364488, 364489, 364490, 364491, G06G 748, G06F 1500

Patent

active

057779015

ABSTRACT:
Method and a system for performing die yield prediction in cooperation with wafer scanning tools. A program analyzes data associated with defects on a wafer substrate, the substrate including multiple layers and multiple die. Files are read that contain defect data for selected layers of the substrate. The defect data includes defect type and defect size information. The defect data is then stacked to identify the layer of first occurrence of each defect and the number, i.e., count, of layers upon which it was redetected. A kill factor is then assigned to each of the defects according to a set of rules, each such rule specifying defect parameters that include layer of first occurrence, redetect count, defect size, and defect type. Failure probabilities, indicative of yield, are then computed for the defects according to the assigned kill factors. The failure probabilites are utilized to calculate the estimated die loss for selected wafers by layer and defect type.

REFERENCES:
patent: 3751647 (1973-08-01), Maeder et al.
patent: 4579455 (1986-04-01), Levy et al.
patent: 4849804 (1989-07-01), Mader
patent: 5274434 (1993-12-01), Morioka et al.
patent: 5317380 (1994-05-01), Allemand
patent: 5475695 (1995-12-01), Caywood
patent: 5544256 (1996-08-01), Brecher et al.
A Wafer Scale fail Bit analysis System for VLSI Memory Yield Improvement, Sakai et al Proc. IEEE 1990 Int. Conference on Microelectronic Test Structures, vol. 3, Mar. 1990, 175-178.
Automatic In-Line Measurement for the Identification of Killer defects, Wilson et al, 1994 IEEE, pp. 5/1-5/8, Apr. 1994.
Automatic Defect Classification System for Patterned Semiconductor Wafers Manufacturing, 68-73.
Role of In-Line Defect Sampling Methodology in Yield Management, Nurani et al, Jul. 1995, International Symposium on Semiconductor Manufacturing, 243-247.
Automatic in-Line to end-of-line defect correlation using FSRAM test structure for quick killer defect identification, Wilson et al, 1994 IEEE, vol. 7, Mar. 94, 160-163.
A Spot-Defect to fault Collapsing Technique, Di et al, 1991 IEEE, pp. 580-583, Jun. 1991.
A fuzzy Logic Expert System for Automatic Defect Classification of Semiconductor Wafer defects, Laria et al, 1994 IEEE, pp. 2100-2106, Jun. 1991.
Simulating IC Reliability with Emphasis on Process-Flaw Related Earlyfailures Moosa et al, IEEE Transactions on Reliability, vol. 44, Nov. 4, 1995, 556-561.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for automated die yield prediction in semicond does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for automated die yield prediction in semicond, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for automated die yield prediction in semicond will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1213513

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.