Method and system for ATM cell multiplexing under constant bit r

Details Method and system for ATM cell multiplexing under constant bit r Method and system for ATM cell multiplexing under constant bit r

1995-12-06

1998-06-23

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370418, 370455, 370459, 370461, H04J 322, H04L 1254

Patent

active

057712344

ABSTRACT:
A method and system are disclosed for scheduling the assignment and writing of cells from cell sources into a outgoing bitstream transmitted from each device of an ATM communications network. The timeslots are organized into fixed length cycles which cycles each have a sequence of N timeslots, where N is an integer >1. Furthermore, each cycle is divided into at least one round comprising a variable length subsequence of the timeslots of the cycle. During each timeslot of a uniform timeslot clock, at least one subset of the sources is identified. Each subset corresponds to a round. One cell from each subset is assigned to, and written into, a respective timeslot of the corresponding round. During each timeslot of the timeslot clock, each of the sources is assigned a priority state depending on how many cells of that source have been previously assigned to timeslots during the current cycle and whether or not that source has a cell available for assignment to a round during that timeslot. The highest priority state assigned to any source during each timeslot is identified. One of the cells of each source with the identified highest priority state are assigned to, and written into, a timeslot of a corresponding round, in a round-robin fashion, to form the subsequence of cells of that round.

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